Effect of source and drain junctions on plasma charging

Misra, D.; Cheung, Kin P.

doi:10.1088/0268-1242/13/5/001

Cited by 7 publications

(1 citation statement)

References 5 publications

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“…8 The injection process could occur through either substrate injection or gate injection, depending upon the potential distribution at the wafer surface during the plasma process. 9 Moreover, the degree of plasma damage is strongly related to the topography of the gate interconnect. The charging effect is amplified by the ratio of the areas of the conducting layer and the gate, the so-called antenna area ratio ͑AR͒.…”

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Plasma-Induced Damage on the Performance and Reliability of Low-Temperature Polycrystalline Silicon Thin-Film Transistors

Chen

Wang

Shieh

et al. 2007

J. Electrochem. Soc.

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We have investigated the impact of plasma-induced damage on the performance and reliability of low-temperature polycrystalline silicon thin-film transistors ͑LTPS TFTs͒. The LTPS TFTs having different antenna structures were used to study the effects of the plasma-etching process. We observed that performance instability occurred for the devices having a relatively large-area antenna. Plasma damage mainly caused nonuniform distribution of the threshold voltages in the LTPS TFTs, presumably because of charge trapping in the gate dielectric during the plasma-etching process. The reliabilities of the LTPS TFTs having larger antenna areas were found to be more degraded under gate-bias stress and hot-carrier stress than those of the samples having smaller antenna areas. Because of their enhanced plasma damage, we speculate that the LTPS TFTs having larger antenna areas possess more trap states in the gate dielectrics. During gate-bias stress or hot-carrier stress, therefore, charges can be injected into the gate dielectric through trap-assisted tunneling, resulting in significant degradation of both the performance and reliability.Polycrystalline silicon thin-film transistors ͑poly-Si TFTs͒ are key devices in flat-panel displays ͑FPDs͒, such as active-matrix liquid crystal displays ͑AMLCDs͒. 1 The high mobility of poly-Si TFTs enables the integration of the pixels and the driving circuit onto a single panel. This yields a light and thin display with a reduced number of connection pins; it also improves both the reliability of the panels and the resolution of the displays. 2 To achieve good process repeatability and precise control over the feature sizes in the insulators, semiconductors, and metals, plasma-etching processes are widely adopted during very-large-scale integration ͑VLSI͒ and poly-Si TFT fabrication. Many reports have highlighted that plasma processing during VLSI manufacturing may induce device degradation. 3,4 When an isolated object comes into contact with plasma, a net negative charge accumulates very rapidly on the object because electrons are the lightest and hottest particles. This situation leads to the buildup of negative potential, called the floating potential ͑V f ͒, with respect to the plasma potential ͑V p ͒. The floating potential continues to increase until the net flux of arriving negative charges on the isolated object is equal to the net flux of positive charges. 5 However, plasma nonuniformity leads to a local imbalance between the flux of the positive and negative charges, causing charge accumulation by the isolated object. 6 If a conducting layer is connected to the gate oxide and then subjected to plasma etching, the layer completely covers the wafer during most of the etching process; charges flow through the layer to balance the local nonuniformity of the charge flux such that no charge accumulates on the layer. When the conducting layer is nearly completely etched, however, the layer eventually becomes discontinuous, leading to the onset of local charge accumulation and damage to...

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