In‐Memory Binary Vector–Matrix Multiplication Based on Complementary Resistive Switches

Ziegler, Tobias; Waser, Rainer; Wouters, Dirk J.; Menzel, Stephan

doi:10.1002/aisy.202070100

Cited by 5 publications

(8 citation statements)

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“…This approach might be facilitated by the use of new memristive devices based on spin (Magnetic Random Access Memory—MRAM) ( Apalkov et al, 2016 ), phase change (Phase Change Memory—PCM) ( Wong et al, 2010 ) or redox reactions (Redox based Resistive Random Access Memory—ReRAM) ( Waser et al, 2009 ). These memristive systems are usually structured in a matrix-like fashion to realize neuromorphic computing systems ( Steinbuch, 1961 , 1963 ; Ziegler et al, 2020 ). Here, ReRAM devices offer several benefits: their low-power, dense integration feasibility and rich device physics open up the opportunity for online learning.…”

Section: Introductionmentioning

confidence: 99%

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

et al. 2021

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With the arrival of the Internet of Things (IoT) and the challenges arising from Big Data, neuromorphic chip concepts are seen as key solutions for coping with the massive amount of unstructured data streams by moving the computation closer to the sensors, the so-called “edge computing.” Augmenting these chips with emerging memory technologies enables these edge devices with non-volatile and adaptive properties which are desirable for low power and online learning operations. However, an energy- and area-efficient realization of these systems requires disruptive hardware changes. Memristor-based solutions for these concepts are in the focus of research and industry due to their low-power and high-density online learning potential. Specifically, the filamentary-type valence change mechanism (VCM memories) have shown to be a promising candidate In consequence, physical models capturing a broad spectrum of experimentally observed features such as the pronounced cycle-to-cycle (c2c) and device-to-device (d2d) variability are required for accurate evaluation of the proposed concepts. In this study, we present an in-depth experimental analysis of d2d and c2c variability of filamentary-type bipolar switching HfO2/TiOx nano-sized crossbar devices and match the experimentally observed variabilities to our physically motivated JART VCM compact model. Based on this approach, we evaluate the concept of parallel operation of devices as a synapse both experimentally and theoretically. These parallel synapses form a synaptic array which is at the core of neuromorphic chips. We exploit the c2c variability of these devices for stochastic online learning which has shown to increase the effective bit precision of the devices. Finally, we demonstrate that stochastic switching features for a pattern classification task that can be employed in an online learning neural network.

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Section: Introductionmentioning

confidence: 99%

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

et al. 2021

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“…[ 1–5 ] As one of the most promising data security techniques, the Hamming distance (HD) computations, that is, the processing of the number of different characters in the corresponding positions between two equal‐length binary strings [ 6 ] is now being intensively applied in the fields of information security encryption, [ 7–10 ] image search and recognition, [ 11–13 ] and binary neural networks. [ 14–18 ] In‐memory computing (IMC) has remarkably enhanced data‐intensive applications, reaching beyond the level of von Neumann computing in terms of processing latency and energy efficiency. [ 19–21 ] Hence, it is imperative to develop a reliable and efficient in‐memory HD computational architecture, which has become a surge of research topic for both academic and industrial communities.…”

Section: Introductionmentioning

confidence: 99%

“…[ 31 ] Compared to unipolar devices, the bipolar resistive switching can overcome the reliability issue as reported in prior studies conducted on the HD computations based on the complementary bipolar switches. [ 14,29,30,32–36 ] However, the conductive filament mechanism inevitably leads to a variation of low resistance state (LRS) and high resistance state (HRS). In fact, the accuracy of the HD computations is highly influenced by the fluctuations of the resistance, because the output of the HD computations is determined by the accumulation of the total reading current in a RRAM array.…”

Section: Introductionmentioning

confidence: 99%

“…In fact, the accuracy of the HD computations is highly influenced by the fluctuations of the resistance, because the output of the HD computations is determined by the accumulation of the total reading current in a RRAM array. [ 14 ] Hence, there is a pressing need for the development of highly reliable and energy efficient in‐memory HD computation devices based on a bipolar switching mechanism that can continuously adapt to the data processing demand. [ 1,37 ]…”

Section: Introductionmentioning

confidence: 99%

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Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

Lin

Liu

et al. 2021

Adv Materials Technologies

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Highly efficient Hamming distance (HD) computations can significantly boost up modern data‐intensive algorithms. However, the traditional complementary metal–oxide–semiconductor devices configured circuits suffer from the huge power consumption with periphery complexity for HD computations. Herein, the implementation of highly reliable and energy efficient in‐memory HD computations in 1 Kb 1‐transistor‐1‐memristor (1T1M) TiN/HfOx/TaOx/TiN array chip is reported. 1T1M devices demonstrate a high on/off ratio of 50, high programming speed of 20 ns, and low energy consumption of 0.224 pJ bit−1. By modulating the 1T1M cell gate and source signal synergistically, the characteristic XOR operations of the binary information are executed in a reliable manner. Importantly, equipped with a stable low resistance state (LRS) distribution (coefficient of variation <11%), the developed 1T1M arrays can implement accurate HD computations between two 8‐bit strings and simultaneously store computing results in the memristors. The complementary studies demonstrate that the stable LRS is attributed to the TaOx built‐in compliance layer which facilitates the transistor surge current reduction during forming and SET, elaborating the significant potential for achieving reliable in‐memory HD computations. Such architecture manifests a 5‐ and 36.89‐fold enhancement of the processing latency and energy efficiency in comparison with latest reports, promoting the fan out of new in‐memory computing applications.

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“…[ 19–21 ] In addition, implementation of XNOR gates using two RRAM devices with complementary encoding has been demonstrated. [ 22 ] However, to implement XNOR cell‐based high‐density arrays, it is necessary to execute the XNOR function using a simple structure and two‐terminal‐based 1S1R devices.…”

Section: Introductionmentioning

confidence: 99%

Hybrid Memory Device (Memory/Selector) with Scalable and Simple Structure for XNOR‐Based Neural Network Applications

Sung

Kim

Kwak

et al. 2021

Adv Elect Materials

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This study investigates the electrical behavior of a hybrid memory device with both memory and selector characteristics. Electrical measurements and simulations indicate that the electrical behaviors (nonvolatile characteristics in Al2O3 layers and volatile characteristics in TiO2 layers) are linked to the stability of the conductive filament (CF) used. The binding energy between the Ag atoms in the CF is crucial for achieving nonvolatile or volatile characteristics. Thus, the hybrid memory device exhibits tunable threshold‐voltage characteristics and a consistent off‐state without requiring an additional selector device. Furthermore, the buffer metal layer between the active electrode and oxide layer affects the filament‐formation process in terms of the switching time. Experimental results show that the buffer layer significantly affects ion motion, such as redox reactions and ion migration. Thus, hybrid memory devices with a Zr buffer layer can solve the voltage–time dilemma, enabling fast and low‐voltage switching. Robust XNOR‐based neural network applications are developed using hybrid memory devices in a cross‐point array with characteristics such as scalability, simple structure, and excellent switching characteristics. By carefully considering the on–off ratio and device variability, hybrid memory devices can ensure reliable operation with a high pattern recognition accuracy in XNOR‐based neural neuromorphic hardware systems.

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In‐Memory Binary Vector–Matrix Multiplication Based on Complementary Resistive Switches

Cited by 5 publications

References 0 publications

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

Utilizing the Switching Stochasticity of HfO2/TiOx-Based ReRAM Devices and the Concept of Multiple Device Synapses for the Classification of Overlapping and Noisy Patterns

Implementation of Highly Reliable and Energy Efficient in‐Memory Hamming Distance Computations in 1 Kb 1‐Transistor‐1‐Memristor Arrays

Hybrid Memory Device (Memory/Selector) with Scalable and Simple Structure for XNOR‐Based Neural Network Applications

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