In-Built N+ Pocket Electrically Doped Tunnel FET With Improved DC and Analog/RF Performance

Abstract

In this paper, we present an in-built N+ pocket electrically doped tunnel FET (ED-TFET) based on the polarity bias concept that enhances the DC and analog/RF performance. The proposed device begins with a MOSFET like structure (n-p-n) with a control gate (CG) and a polarity gate (PG). The PG is biased at −0.7 V to induce a P+ region at the source side, leaving an N+ pocket between the source and the channel. This technique yields an N+ pocket that is realized in the in-built architecture and removes the need for additional chemical doping. Calibrated 2-D simulations have demonstrated that the introduction of the N+ pocket yields a higher ION and a steeper average subthreshold swing when compared to conventional ED-TFET. Further, a local minimum on the conduction band edge (EC) curve at the tunneling junction is observed, leading to a dramatic reduction in the tunneling width. As a result, the in-built N+ pocket ED-TFET significantly improves the DC and analog/RF figure-of-merits and, hence, can serve as a better candidate for low-power applications.

Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET

“…However, realizing this narrow N+ doped pocket is a technological challenge [ 15 , 16 , 17 , 18 ]. Based on the polarity bias concept, we have recently reported a theoretical device structure of an in-built N + pocket electrically doped (ED) tunnel FET, which provides a possible technique to overcome the difficulties in realizing a highly doped narrow pocket [ 19 ].…”

“…We can see from Figure 1 b,d that the main difference between these two structures is the formation of the drain region. In the conventional in-built N + pocket ED-TFET, the N+ drain region is uniformly doped by ion implantation [ 19 ]. However, in the proposed device with an ED drain, the drain region is electrically doped based on the polarity bias concept, and it introduces a new design parameter L gap , which is the length of the gap between the channel and the drain.…”

Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance

“…In addition to these advantages, TFETs have two major disadvantages, namely low on-state current (I ON ) and ambipolarity during switching [2]. In order to overcome I ON and the ambipolar issue, we have recently proposed an in-built N + pocket electrically doped TFET (ED-TFET) with and without an electrically doped drain, using the concept of polarity bias [3,4]. An in-built N + pocket ED-TFET structure is very similar to a PNPN TFET structure, except that it does not require additional chemical doping for the narrow N + pocket [5,6].…”

Novel L‐shaped drain dual‐gateSiGe MOSFETforhigh‐frequency, low power applications

“…The Tunnel-FET (TFET) was designed to meet the CMOS scaling challenges and current industry expectations, and it has emerged as a viable solution to major constraints associated with downscaling, such as the thermionic limit of sub-threshold swing and substantial off-state leakage. 12,13 For electron transport in this device, band to band tunneling (BTBT) is mostly dominant over traditional thermal injection. As a result, this transistor has a steeper sub-threshold swing and a low-off current.…”