Controlling Drain Side Tunneling Barrier Width in Electrically Doped PNPN Tunnel FET

Abstract

In this paper, we propose and investigate an electrically doped (ED) PNPN tunnel field effect transistor (FET), in which the drain side tunneling barrier width is effectively controlled to obtain a suppressed ambipolar current. We present that the proposed PNPN tunnel FETs can be realized without chemically doped junctions by applying the polarity bias concept to a doped N+/P− starting structure. Using numerical device simulations, we demonstrate how the tunneling barrier width on the drain side can be influenced by several design parameters, such as the gap length between the channel and the drain (Lgap), the working function of the polarity gate, and the dielectric material of the spacer. The simulation results show that an ED PNPN tunneling FET with an ED drain, which has been explored for the first time, exhibits a low ambipolar current of 5.87 × 10−16 A/µm at a gap length of 20 nm. The ambipolar current is reduced by six orders of magnitude compared to that which occurs with a conventional ED PNPN tunnel FET with a uniformly doped drain, while the average subthreshold slope and the ON state and OFF state currents remained nearly identical.

Electrically Doped PNPN Tunnel Field-Effect Transistor Using Dual-Material Polarity Gate with Improved DC and Analog/RF Performance

“…In addition to these advantages, TFETs have two major disadvantages, namely low on-state current (I ON ) and ambipolarity during switching [2]. In order to overcome I ON and the ambipolar issue, we have recently proposed an in-built N + pocket electrically doped TFET (ED-TFET) with and without an electrically doped drain, using the concept of polarity bias [3,4]. An in-built N + pocket ED-TFET structure is very similar to a PNPN TFET structure, except that it does not require additional chemical doping for the narrow N + pocket [5,6].…”