Impurity Redistribution and Junction Formation in Silicon by Thermal Oxidation

Atalla, M. M.; Tannenbaum, Eileen

doi:10.1002/j.1538-7305.1960.tb03947.x

Cited by 78 publications

(13 citation statements)

References 2 publications

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“…(1) The same parabolic rate "constant" IS obtained for (5) much better agreement is obtained between actual and calculated film thicknesses than that obtained on basis of a pure parabolic law;…”

Section: Discussionmentioning

confidence: 58%

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Separation of the Linear and Parabolic Terms in the Steam Oxidation of Silicon

Pliskin¹

1966

IBM J. Res. & Dev.

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Using accurate film thickness measurements, it was found possible to separate linear and parabolic terms in the steam oxidation of silicon, and thus obtain much more precise expressions for the thermal oxidation under different conditions. The combined linear-parabolic relation was found to be applicable to various crystallographic orientations. The pure parabolic "constant" obtained from this relation was the same for different crystal orientations, but the linear term in the relation was found to be very surface sensitive. By these techniques, more accurate parabolic rate "constants" can be obtained and the linearity of the log k vs liT plot can be extended to much lower temperatures. The activation energy of the parabolic term for steam oxidation was found to be only 16 kcal/mole, The effect of neglecting the linear term in various methods of computing the parabolic rate is discussed.

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Section: Discussionmentioning

confidence: 58%

“…This may not be strictly correct as will be discussed later. In practice, we can write the equation: (5) If k 2 were directly proportional to the pressure, than n in the above equation would be equal to 1. From the data given in Table 4, n was found to be 1.01.…”

Section: • Oxidation At Low Water Vapor Pressurementioning

confidence: 98%

Separation of the Linear and Parabolic Terms in the Steam Oxidation of Silicon

Pliskin¹

1966

IBM J. Res. & Dev.

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“…This process re-distributed the Sn in the Ge 1Àx Sn x -oxide/Ge 1Àx Sn x stack, similar to impurity redistribution near the Si oxide and Si interface during thermal oxidation. 20,21 As discussed in Grove et al, this redistribution can be explained by the small segregation coefficient of the impurities, a ratio of the equilibrium concentrations of impurities in the substrate to that in the oxide layer; in such cases, the impurity concentration at the surface decreases relative to that inside the substrate. 22 However, during re-distribution of Sn in thermal oxidation, the Sn content near the Ge 1Àx Sn x surface did not decrease after thermal oxidation, despite the significant Sn migration into the Ge 1Àx Sn x -oxide layer.…”

mentioning

confidence: 95%

Formation of high-quality oxide/Ge1−xSnx interface with high surface Sn content by controlling Sn migration

Kato

Taoka

Asano

et al. 2014

Applied Physics Letters

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In this paper, we investigated how Sn migrated during annealing for Ge1−xSnx at its surface and in its interior, as well as the Ge oxide formation on Ge1−xSnx with controlling surface oxidation. After oxidation at 400 °C, X-ray photoelectron spectroscopy and X-ray diffraction measurements revealed Sn migration from inside the epitaxial Ge1−xSnx layer to its surface. Annealing was not the primary cause of significant Sn migration; rather, it was caused mostly by oxidation near the Ge1−xSnx surface. This process formed a Ge1−xSnx oxide with a very high Sn content of 30%, inducing a wide hysteresis loop in the capacitance–voltage characteristics of its corresponding MOS device. We also found that forming a thin GeO2 layer by using a deposition method that controls Ge surface oxidation produced low densities of interface states and slow states. From these results, we conclude that controlling Sn migration is critical to forming a high-quality Ge1−xSnx gate stack.

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“…However, due to the presence of an oxide layer on the silicon surface during the soak step, the concentration of phosphorus in the silicon has increased where it contacts the oxide layer due to a segregation coefficient greater than unity. 12,13 In contrast, the concentration of boron decreases at the siliconoxide interface due to a segregation coefficient less than unity. The segregation coefficient represents a comparison of the equilibrium solubility of each dopant in silicon versus in silicon dioxide, which will dictate the concentrations on each side of the interface that will yield equal Gibbs free energy values of the dopant at the interface.…”

Section: A Simulation Of Diffusion and Resistancementioning

confidence: 89%

A method for temperature profile measurement of silicon wafers in high-temperature environments

Appapillai

Sachs

2011

Journal of Applied Physics

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This paper describes the development of a method to characterize the temperature profile of silicon wafers in high-temperature environments. Monocrystalline wafers are implanted on one surface with B and P ions, which diffuse into the wafer at different rates based on the temperature-dependent diffusivity of the ions during a 30 min soak in the high-temperature environment between 1000 and 1400 °C. The use of two different dopant species, instead of one, yields higher sensitivity of the measured resistance to changes in temperature in this high-temperature range. The ρ-T relation is simulated using TSUPREM-4 and calibrated using a furnace of known temperature. The final sheet resistance varies spatially between 50 and 250 Ω/sq, and can be related to the temperature of each part of the wafer during the soak step, with a sensitivity of ∼0.5 Ω/°C, and a two-dimensional temperature map can be extracted. The method is demonstrated on wafers by characterizing the hot zone of a high-temperature furnace.

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Impurity Redistribution and Junction Formation in Silicon by Thermal Oxidation

Cited by 78 publications

References 2 publications

Separation of the Linear and Parabolic Terms in the Steam Oxidation of Silicon

Separation of the Linear and Parabolic Terms in the Steam Oxidation of Silicon

Formation of high-quality oxide/Ge1−xSnx interface with high surface Sn content by controlling Sn migration

A method for temperature profile measurement of silicon wafers in high-temperature environments

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