Formation of high-quality oxide/Ge1−xSnx interface with high surface Sn content by controlling Sn migration

Abstract

In this paper, we investigated how Sn migrated during annealing for Ge1−xSnx at its surface and in its interior, as well as the Ge oxide formation on Ge1−xSnx with controlling surface oxidation. After oxidation at 400 °C, X-ray photoelectron spectroscopy and X-ray diffraction measurements revealed Sn migration from inside the epitaxial Ge1−xSnx layer to its surface. Annealing was not the primary cause of significant Sn migration; rather, it was caused mostly by oxidation near the Ge1−xSnx surface. This process formed a Ge1−xSnx oxide with a very high Sn content of 30%, inducing a wide hysteresis loop in the capacitance–voltage characteristics of its corresponding MOS device. We also found that forming a thin GeO2 layer by using a deposition method that controls Ge surface oxidation produced low densities of interface states and slow states. From these results, we conclude that controlling Sn migration is critical to forming a high-quality Ge1−xSnx gate stack.

Growth and applications of GeSn-related group-IV semiconductor materials

“…Therefore, Sn atoms often precipitate in a GeSn(Si) layer and segregate on a GeSn(Si) surface during deposition and annealing after GeSn(Si) layer formation (referred to as PDA) [20, 21, 94]. Furthermore, high deposition temperatures and PDA at high temperatures induce Sn desorption from the surface [20, 21, 95]. These results mean that MOS technology for an Sn-based alloy is a challenging technology because a technique to precisely control the physical behaviors of Sn atoms during layer formation and PDA must be established.…”

“…However, the robustness of the substitutional Sn atoms during thermal oxidation of a Ge 1− x Sn x surface has not been investigated yet. Therefore, we investigated the physical behaviors of Sn atoms during thermal oxidation and the impact of thermal oxidation on the electrical interface properties [21, 95]. …”

“…To overcome these problems, we have established a CVD method for formation of a thin Ge-oxide layer on a Ge substrate, which allows for controlling thickness on the atomic scale and suppression of Ge surface oxidation (GSO) because of the self-limiting adsorption of tetraethoxy-germanium on a Ge substrate and exposure of H 2 O, similar to the atomic layer deposition method [95]. Figures 11(a) and (b) compare the C – V characteristics of the Al/Al 2 O 3 /Ge 0.924 Sn 0.076 /Ge MOS capacitors with a thermal Ge 1− x Sn x -oxide layer formed at 400 °C and a GSO-controlled layer, respectively, between the Al 2 O 3 and Ge 0.924 Sn 0.076 layers.…”

“…1 MHz C–V characteristics of the Al/Al 2 O 3 /Ge 0.924 Sn 0.076 /Ge MOS capacitors with (c) a thermal Ge 1− x Sn x oxide layer and (d) a GSO-controlled layer. Here, all C – V curves were measured at 100 K. Reprinted with permission from [95]. Copyright 2014, American Institute of Physics.…”

70 °C synthesis of high-Sn content (25%) GeSn on insulator by Sn-induced crystallization of amorphous Ge

“…6 Besides, GeSn is a promising buffer layer for fabricating strained-Ge and other functional materials because of the tunability of the lattice constant by varying the Sn composition. [7][8][9] Since the solubility limit of Sn in Ge is as low as 1%, researchers have developed nonequilibrium low-temperature process using molecular-beam epitaxy (MBE), 10-16 chemical-vapor deposition (CVD), [17][18][19] or ion implantation. 20 These techniques have enabled GeSn with high Sn compositions up to 34%, leading to high-speed metal-oxide-semiconductor field-effect transistors 21,22 and high-sensitivity infrared photodetectors.…”