Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

Ueno, Hideki; Kitamaru, D.; Morikawa, Katsumi; Tanaka, Masayasu; Miura-Mattausch, Mitiko; Mattausch, Hans Jürgen; Kumashiro, S.; Yamaguchi, Tomohiro; Yamashita, K.; Nakayama, Noriaki

doi:10.1109/ted.2002.803633

Cited by 17 publications

(8 citation statements)

References 12 publications

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“…Then the 1D (for large device) threshold voltage is obtained from 1D numerical solution of the Poisson's equation in the channel region (a very fast and accurate algorithm described in [9] is used here). This voltage is corrected for short channel and DIBL effects by means of analytical approximations [10,11], with effective gate length taken into account. The Poisson's equation is solved three times, for zero body bias and for two nonzero VBS values.…”

Section: B Cad Toolsmentioning

confidence: 99%

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

Kuźmicz

Piwowarska

Pfitzner

et al. 2008

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering

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A special CAD toolset for process, device and circuit statistical simulation is described. Variability is introduced in the process parameter space, not in the space of parameters of the circuit components. As a result, complex dependencies and correlations between process parameters and circuit performance are taken into account in a realistic way. Application to analysis of static current consumption in deep submicron CMOS digital circuits is demonstrated 1 .

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Section: B Cad Toolsmentioning

confidence: 99%

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

Kuźmicz

Piwowarska

Pfitzner

et al. 2008

2008 IEEE Region 8 International Conference on Computational Technologies in Electrical and Electronics Engineering

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“…17 shows the pocket-implant model of HiSIM. The lateral impurity profile is approximated by a linearly decreasing function with the maximum concentration of N subp and the extension length L p (10). It happens that the linearly decreasing function for the pocket is not sufficient but that a pocket tail has to be considered as shown in the figure schematically.…”

Section: Reliability Of Model Parametersmentioning

confidence: 99%

Analysis of Technology Variations in Advanced MOSFETS with the Surface-Potential-Based Compact Model HiSIM

Miura-Mattausch¹,

Sadachika²,

Miyake³

et al. 2007

ECS Trans.

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Technology variations are becoming a serious and most likely dominant problem as the MOSFET size is scaled down to the 65nm node and below. Dealing with this problem requires an understanding of the origin of these variations and their precise connection to the MOSFET's engineering parameters. Here an analysis of the suitability of the advanced surface-potential-based MOSFET model HiSIM for this purpose is reported. With the HiSIM model, the variations of the MOSFET characteristics are analyzed based on their physical origins, namely the variations of the fabrication technology. In particular, it is also shown that measurements for characterizing the RF performances of the MOSFET provide valuable information about microscopic fabrication-technology variations.

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“…The V th dependence on the bulk voltage (V bs ) gives important information about the condition beneath the gate oxide. [11][12][13] We exploit the feature for extracting the device parameters. However, the V th description for the SOI-MOSFET is not single but differs for different V bs values applied.…”

Section: For the Task (2)mentioning

confidence: 99%

Complete Surface-Potential-Based Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor Model for Circuit Simulation

Kitamaru¹,

Uetsuji²,

Sadachika³

et al. 2004

Jpn. J. Appl. Phys.

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The circuit simulation model Hiroshima-university STARC IGFET Model silicon-on-insulator (HiSIM-SOI) for the fully depleted SOI metal-oxide-semiconductor field-effect-transistor (MOSFET) is developed based on the surafce-potential description. To include all device features of the SOI-MOSFET explicitly, the surface potential values not only at the SOI surface but also the back side, as well as the bulk back-gate are solved iteratively. The total iteration for the potential calculation requires only about twice as much calculation time as the bulk-MOSFET case, solving ony at the surface. The model reproduces measured I-V characteristics within numerical accuracy, and is proved stable circuit convergence.

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Impurity-profile-based threshold-voltage model of pocket-implanted MOSFETs for circuit simulation

Cited by 17 publications

References 12 publications

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

CAD tools for analysis of process variability effects in deep submicron CMOS circuits

Analysis of Technology Variations in Advanced MOSFETS with the Surface-Potential-Based Compact Model HiSIM

Complete Surface-Potential-Based Fully-Depleted Silicon-on-Insulator Metal-Oxide-Semiconductor Field-Effect-Transistor Model for Circuit Simulation

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