Improving memory bank-level parallelism in the presence of prefetching

Lee, Chang Joo; Narasiman, Veynu; Mutlu, Onur; Patt, Yale N.

doi:10.1145/1669112.1669155

Cited by 109 publications

(65 citation statements)

References 18 publications

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“…An application's memory access characteristics can be evaluated using four metrics: a) memory intensity, measured as the number of last-level cache misses per thousand instructions (MPKI) [16,42]; b) write intensity, measured as the portion of write misses (WR%) out of all cache misses; c) bank-level parallelism (BLP), measured as the average number of banks with outstanding memory requests, when at least one other outstanding request exists [50,65]; d) row-buffer locality (RBL), measured as the average hit rate of the row buffer across all banks [64,77].…”

Section: Memory Access Characteristics Of Persistent Applicationsmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Byte-addressable nonvolatile memories promise a new technology, persistent memory, which incorporates desirable attributes from both traditional main memory (byte-addressability and fast interface) and traditional storage (data persistence). To support data persistence, a persistent memory system requires sophisticated data duplication and ordering control for write requests. As a result, applications that manipulate persistent memory (persistent applications) have very different memory access characteristics than traditional (non-persistent) applications, as shown in this paper. Persistent applications introduce heavy write traffic to contiguous memory regions at a memory channel, which cannot concurrently service read and write requests, leading to memory bandwidth underutilization due to low bank-level parallelism, frequent write queue drains, and frequent bus turnarounds between reads and writes. These characteristics undermine the high-performance and fairness offered by conventional memory scheduling schemes designed for non-persistent applications.Our goal in this paper is to design a fair and high-performance memory control scheme for a persistent memory based system that runs both persistent and non-persistent applications. Our proposal, FIRM, consists of three key ideas. First, FIRM categorizes request sources as non-intensive, streaming, random and persistent, and forms batches of requests for each source. Second, FIRM strides persistent memory updates across multiple banks, thereby improving bank-level parallelism and hence memory bandwidth utilization of persistent memory accesses. Third, FIRM schedules read and write request batches from different sources in a manner that minimizes bus turnarounds and write queue drains. Our detailed evaluations show that, compared to five previous memory scheduler designs, FIRM provides significantly higher system performance and fairness.

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Section: Memory Access Characteristics Of Persistent Applicationsmentioning

confidence: 99%

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Zhao

Mutlu²,

Xie

2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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“…Row buffer locality and bank-level parallelism: Several memory request scheduling techniques for improving bank-level parallelism and row buffer locality [1,22,23,[25][26][27]31,33,39,45] have been proposed. In particular, the work by Hassan et al [13] quantifies the trade-off between BLP and row locality for multi-core systems, and concludes that bank-level parallelism is more important.…”

Section: Related Workmentioning

confidence: 99%

Orchestrated scheduling and prefetching for GPGPUs

Jog

Kayıran

Mishra

et al. 2013

Proceedings of the 40th Annual International Symposium on Computer Architecture

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136

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In this paper, we present techniques that coordinate the thread scheduling and prefetching decisions in a General Purpose Graphics Processing Unit (GPGPU) architecture to better tolerate long memory latencies. We demonstrate that existing warp scheduling policies in GPGPU architectures are unable to effectively incorporate data prefetching. The main reason is that they schedule consecutive warps, which are likely to access nearby cache blocks and thus prefetch accurately for one another, back-to-back in consecutive cycles. This either 1) causes prefetches to be generated by a warp too close to the time their corresponding addresses are actually demanded by another warp, or 2) requires sophisticated prefetcher designs to correctly predict the addresses required by a future "far-ahead" warp while executing the current warp.We propose a new prefetch-aware warp scheduling policy that overcomes these problems. The key idea is to separate in time the scheduling of consecutive warps such that they are not executed back-to-back. We show that this policy not only enables a simple prefetcher to be effective in tolerating memory latencies but also improves memory bank parallelism, even when prefetching is not employed. Experimental evaluations across a diverse set of applications on a 30-core simulated GPGPU platform demonstrate that the prefetch-aware warp scheduler provides 25% and 7% average performance improvement over baselines that employ prefetching in conjunction with, respectively, the commonlyemployed round-robin scheduler or the recently-proposed two-level warp scheduler. Moreover, when prefetching is not employed, the prefetch-aware warp scheduler provides higher performance than both of these baseline schedulers as it better exploits memory bank parallelism.

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“…Delaying a memory-intensive application in lieu of a memory non-intensive application with inherently small memory stall times can improve both system performance and fairness [26,19,8,15,16]. As we show in Section 6, demand-boosting enables performance benefits from prefetching that are not possible without it.…”

Section: Demand Boostingmentioning

confidence: 92%

Prefetch-aware shared resource management for multi-core systems

Ebrahimi

Lee

Mutlu

et al. 2011

SIGARCH Comput. Archit. News

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Chip multiprocessors (CMPs) share a large portion of the memory subsystem among multiple cores. Recent proposals have addressed high-performance and fair management of these shared resources; however, none of them take into account prefetch requests. Without prefetching, significant performance is lost, which is why existing systems prefetch. By not taking into account prefetch requests, recent shared-resource management proposals often significantly degrade both performance and fairness, rather than improve them in the presence of prefetching.This paper is the first to propose mechanisms that both manage the shared resources of a multi-core chip to obtain highperformance and fairness, and also exploit prefetching. We apply our proposed mechanisms to two resource-based management techniques for memory scheduling and one source-throttling-based management technique for the entire shared memory system. We show that our mechanisms improve the performance of a 4-core system that uses network fair queuing, parallelism-aware batch scheduling, and fairness via source throttling by 11.0%, 10.9%, and 11.3% respectively, while also significantly improving fairness.

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Improving memory bank-level parallelism in the presence of prefetching

Cited by 109 publications

References 18 publications

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

FIRM: Fair and High-Performance Memory Control for Persistent Memory Systems

Orchestrated scheduling and prefetching for GPGPUs

Prefetch-aware shared resource management for multi-core systems

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