Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

Song, Young Suh; Kim, Jang Hyun; Kım, Garam; Kim, Hyun‐Min; Kim, Sangwan; Park, Byung‐Gook

doi:10.1109/jeds.2020.3038391

Cited by 30 publications

(11 citation statements)

References 36 publications

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“…In previous research, the advanced bandgap-engineered TaN/Al 2 O 3 /HfO 2 /SiO 2 /Si (BE-TAHOS) structure has been investigated for a faster erasing speed and larger memory window by incorporating Si 3 N 4 at the tunneling oxide layer [37][38][39][40][41][42][43][44]. By utilizing this BE-TAHOS structure [34][35][36] and applying Al 2 O 3 at the tunneling layer, the advanced structure of TaN/Al 2 O 3 /HfO 2 /SiO 2 /Al 2 O 3 /SiO 2 /Si (TAHOAOS) is designed for NOR flash memory.…”

Section: Device Structure and Model Physics 21 Structure Of The Promentioning

confidence: 99%

“…Consequently, it has been demonstrated that the retention characteristics can be significantly improved in a high-κ-based NOR flash memory device by utilizing the advanced tunneling layers with SiO 2 /Al 2 O 3 /SiO 2 on the tunnel field effect transistor (TFET) structure, which has been broadly studied for low power application [37][38][39][40][41][42][43][44]. From an array perspective, it has been demonstrated that the proposed memory device structure is also able to inhibit the programming in unselected cells by bottom gate effect.…”

Section: Introductionmentioning

confidence: 99%

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Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Song

Park

2021

Micromachines

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For improving retention characteristics in the NOR flash array, aluminum oxide (Al2O3, alumina) is utilized and incorporated as a tunneling layer. The proposed tunneling layers consist of SiO2/Al2O3/SiO2, which take advantage of higher permittivity and higher bandgap of Al2O3 compared to SiO2 and silicon nitride (Si3N4). By adopting the proposed tunneling layers in the NOR flash array, the threshold voltage window after 10 years from programming and erasing (P/E) was improved from 0.57 V to 4.57 V. In order to validate our proposed device structure, it is compared to another stacked-engineered structure with SiO2/Si3N4/SiO2 tunneling layers through technology computer-aided design (TCAD) simulation. In addition, to verify that our proposed structure is suitable for NOR flash array, disturbance issues are also carefully investigated. As a result, it has been demonstrated that the proposed structure can be successfully applied in NOR flash memory with significant retention improvement. Consequently, the possibility of utilizing HfO2 as a charge-trapping layer in NOR flash application is opened.

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Section: Device Structure and Model Physics 21 Structure Of The Promentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Song

Park

2021

Micromachines

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“…Currently, the search and study of materials with high dielectric constanthigh-k dielectricsfor use as a gate dielectric in field-effect transistors, MOS structures, − in III–V semiconductor transistors, active medium in flash memory devices, − as well as in nonvolatile elements of Resistive Random Access Memory (ReRAM) continues. The mechanism of charge transport in high-k dielectrics is the subject of active study. − It was shown that charge transport in dielectrics occurs through defects (traps), i.e., levels localized in the band gap, capable of changing the charge state.…”

Section: Introductionmentioning

confidence: 99%

Determination of Type and Concentration of Traps in Nanoscale-Thick HfO₂ Films Applicable for Gate Dielectric Stacks

Dementeva,

Dementev,

Yagovkina

et al. 2023

ACS Appl. Nano Mater.

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Nanoscale-thick films, including high-k dielectrics, are an essential element of modern electronic devices (e.g., transistors based on III–V semiconductors). In this regard, the development of techniques for studying the electronic properties of such nano-objects is an important task. In this work, we propose a technique that makes it possible to determine the presence of trap levels, their concentration, and the activation energy for films up to 40 nm thick. The mechanism of charge transport in high-k dielectrics, such as HfO2, is the subject of active study. We investigated thin hafnia films grown on the Si surface with TEMAH-H2O or Hf(thd)4-O2 precursor systems. It was shown by X-ray photoemission spectroscopy that the TEMAH-H2O sample was grown with oxygen deficiency. On the Hf(thd)4-O2 sample, the SiO2 sublayer between hafnia and substrate was formed, which was confirmed by Kelvin probe microscopy and X-ray reflectivity studies. This SiO2 sublayer significantly affects the charge dissipation. Diffusion in the lateral direction along the SiO2 sublayer has a higher diffusion coefficient than in the HfO2 layer, but the presence of the SiO2 sublayer reduces the level of charge leakage to the substrate. The activation energies for hole traps and electron traps were found to be E a ≈ 0.46 ± 0.03 and 0.37 ± 0.03 eV for the TEMAH-H2O sample and E a ≈ 0.22 ± 0.05 and 0.16 ± 0.04 eV for the Hf(thd)4-O2 sample, respectively. It was also shown that the process of positive charge localization occurs faster than negative charge localization. Electron localization leads to a decrease of the intensity of the 2.65 eV CL band, associated with oxygen vacancies.

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“…To be precise, the term "2 nanometer" is not associated with the precise physical feature of a typical transistor, but is a commercial term utilized by the chip manufacturing industry based on transistor density, operational speed, and power consumption [3]. As the device size decreases, MOS devices with multi-gate structures are increasingly employed for integrated circuits, including FinFET [4], gate-all-around (GAA) [5,6], and nanosheet-based three-dimensional devices [7,8]. Additionally, various semiconductor materials have been utilized for high-performance semiconductor devices, including high-k hafnium oxide and 2D semiconductor materials [9,10], etc.…”

Section: Introductionmentioning

confidence: 99%

Auger Electron Spectroscopy (AES) and X-ray Photoelectron Spectroscopy (XPS) Profiling of Self Assembled Monolayer (SAM) Patterns Based on Vapor Deposition Technique

et al. 2022

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It is crucial to develop novel metrology techniques in the semiconductor fabrication process to accurately measure a film’s thickness in a few nanometers, as well as the material profile of the film. Highly uniform trichlorosilane (1H,1H,2H,2H-perfluorodecyltrichlorosilane, FDTS) derived SAM film patterns were fabricated by several conventional semiconductor fabrication methods combined, including photolithography, SAM vapor deposition, and the lift-off technique. Substantial information can be collected for FDTS SAM film patterns when Auger electron spectroscopy (AES) and X-ray photoelectron spectroscopy (XPS) techniques are incorporated to investigate this material. Precise two-dimensional (2D) FDTS SAM film patterns were reconstructed through mapping analysis of corresponding elements and chemical state peaks by AES and XPS. Additionally, three-dimensional (3D) FDTS SAM film patterns were also reconstructed layer by layer through gas cluster ion beam (GCIB) etching and XPS analysis. These characterization results demonstrate that FDTS SAM film patterns based on the vapor deposition method are highly uniform because the vacuum and precise gas-delivery system exclude ambient environmental interference efficiently and ensure reaction process repeatability. AES and XPS techniques could be used for metrology applications in the semiconductor process with high-quality SAM microstructures and nanostructures.

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Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

Cited by 30 publications

References 36 publications

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Determination of Type and Concentration of Traps in Nanoscale-Thick HfO₂ Films Applicable for Gate Dielectric Stacks

Auger Electron Spectroscopy (AES) and X-ray Photoelectron Spectroscopy (XPS) Profiling of Self Assembled Monolayer (SAM) Patterns Based on Vapor Deposition Technique

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Improvement in Self-Heating Characteristic by Incorporating Hetero-Gate-Dielectric in Gate-All-Around MOSFETs

Cited by 30 publications

References 36 publications

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Retention Enhancement in Low Power NOR Flash Array with High-κ–Based Charge-Trapping Memory by Utilizing High Permittivity and High Bandgap of Aluminum Oxide

Determination of Type and Concentration of Traps in Nanoscale-Thick HfO2 Films Applicable for Gate Dielectric Stacks

Auger Electron Spectroscopy (AES) and X-ray Photoelectron Spectroscopy (XPS) Profiling of Self Assembled Monolayer (SAM) Patterns Based on Vapor Deposition Technique

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Determination of Type and Concentration of Traps in Nanoscale-Thick HfO₂ Films Applicable for Gate Dielectric Stacks