Improvement in Gate Insulation in InP Hot Electron Transistors for High Transconductance and High Voltage Gain

Abstract

In this paper, the device characteristics of an InP hot electron transistor with improved gate insulation are reported. The breakdown voltage of the gate was increased from 0.5 to 2.5 V by increasing the distance between the gate and the electron transport region. Consequently, the appropriate gate bias at which a clear transconductance peak could be observed was applied. The transconductance was increased from 55 to 130 mS/mm. When the output conductance was reduced, the open circuit voltage gain was about 10.

Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with High Current Density

“…This increase corresponds to a current density of 6 MA/cm 2 . We calculated the drain current density by using Tsu and Esaki's model 7,14) with tunneling and quantum reflection at the heterointerface. Because the space charge effect of the transit electrons is not considered in this calculation, this calculation is simpler and less time-consuming than the Monte Carlo simulation.…”

“…[5][6][7][8][9] The electrons extracted from the source region are expected to transport in the channel without any scattering, because of the undoped channel. We can use an InP/InGaAs heterostructure because the device structure is vertical.…”

Reduction of Output Conductance in Vertical InGaAs Channel Metal–Insulator–Semiconductor Field-Effect Transistor Using Heavily Doped Drain Region

“…[6][7][8][9][10][11] Therefore, a vertical InGaAs channel metal-insulator-semiconductor field-effect transistor (MISFET) with an InP/InGaAs heterostructure launcher and an undoped channel was proposed. [6][7][8][9][10][12][13][14][15] To realize high-speed operation of the proposed device, the device was fabricated as shown in Fig. 1(a).…”

“…The fabricated device operated at a high drain current density and included a 15-nm-wide channel mesa structure. 12,13) However, the output conductance (g o ) of the device was large, and this large g o was a problem because it decreased the cutoff frequency and open circuit voltage gain (g m =g o , where g m denotes the transconductance of the device).…”

Fabrication of Vertical InGaAs Channel Metal–Insulator–Semiconductor Field Effect Transistor with a 15-nm-Wide Mesa Structure and a Drain Current Density of 7 MA/cm2

“…[3][4][5] Therefore, we proposed a vertical InGaAs channel metal-insulator-semiconductor field effect transistor (MISFET) with an InP/InGaAs heterostructure launcher and an intrinsic channel. [6][7][8][9][10] To realize a short charging time as well as a short transit time, a narrow channel with high current density is required. When the current density exceeds 1 MA/cm 2 and the mesa width, which corresponds to the channel thickness in a lateral FET, is 20 nm, the MISFET can be expected to operate at a cutoff frequency higher than 1 THz.…”