Improved single-stage kickback-rejected comparator for high speed and low noise flash ADCs

An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

“…Moreover, in such a structure, at high frequencies (beyond the unity gain frequency), the integration of the output currents by the capacitance of the nodes determines the output voltages rather than the DC gain of the amplifier. (b) Despite the thought which implies that the common mode voltage of the output nodes must be kept constant [4,5], connecting the nodes to the ground and waiting for the winner side to charge up, defines the required time for the evaluation of the winner, exactly according to the process corners. Because in fast or slow corners the charging procedure becomes fast or slow respectively, and the most important outcome is, that in all conditions the latching sequence is postponed until the winner side charges up to turn on the corresponding current mirror.…”

“…Because in fast or slow corners the charging procedure becomes fast or slow respectively, and the most important outcome is, that in all conditions the latching sequence is postponed until the winner side charges up to turn on the corresponding current mirror. In some approaches more than one signal is required to determine the time period of different sequences (resetting, evaluating and latching) [1,[3][4][5][6]. Meanwhile in this structure there is no need for an additional controlling signal to determine the start and stop time of the evaluation period.…”

“…Section 3 describes the main structure, and then the offset cancellation method is discussed in Sect. 4. Simulation results are illustrated in Sect.…”

A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

“…Single-Stage kickback-rejected comparators are proposed in [6], [7] and [8] in which a single hardware is scheduled for three operations: reset, pre-amplification and latch. Cascode structure of NMOS devices alongside the muting shared capacitor is utilized to reduce the kickback effect of output latch on analog inputs.…”

“…Cascode structure of NMOS devices alongside the muting shared capacitor is utilized to reduce the kickback effect of output latch on analog inputs. Two, in [6] and [7], and three, in [8], control signals are required for time scheduling in which the amplitude of control signals are also reduced in low-noise comparator of [8]. Although the proposed comparators are optimized for area and power consumption to be repeatedly used in flash structures, but the ability of tracking high-speed inputs are not considered.…”