An ultra high-speed high-resolution low-offset low-power voltage comparator with a reliable offset cancellation method for high-performance applications in 0.18 µm CMOS technology

Abstract

In this paper a novel structure is presented as a voltage comparator, and a reliable offset cancellation technique is utilized as well. Moreover a comprehensive post layout simulation method is described to evaluate a vast verity of comparators in order to find out whether the designed structure will operate properly in the post fabrication (solid state) tests or not. A single stage architecture with a simple readout circuit leads to a low-offset lowpower high-speed high-resolution comparator which qualifies for VLSI applications such as image sensors. Applying the reliable offset cancellation technique makes it qualified for high performance applications like high-speed high-resolution ADCs. The proposed comparator is simulated through the mentioned method in 0.18 lm standard CMOS technology, and 0.5 mV of accuracy in 1 G sample per second is obtained with a power consumption of 110 lW (150 lW with offset cancellation circuit) where an introduced offset of about 10 mV is cancelled to lower than 220 lV as well.

A High-Speed Low-Offset Double Tail Dynamic Comparator for Low-Power Applications

“…Dynamic power of the comparator mainly depends on the supply voltage (VDD), load capacitance (C L ) and maximum input signal frequency (f in ). According to equation (8), the power consumption increases as the result of an increase in power supply.…”