An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process

Huang, Sen; Diao, Shengxi; Lin, Fujiang

doi:10.1007/s10470-016-0811-4

Cited by 29 publications

(8 citation statements)

References 28 publications

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“…For typical dark currents of 20 pA at a reverse bias of 5 V, the electrical power needed during the integration and recovery times is on the order of 100 pW per class, or about 1 aJ/inference/class. Additional energy is needed to monitor the detectors, which could be accomplished with high speed comparators, which have subns response times and require ∼100 fJ/conversion. Even with this additional energy cost, the performance compares favorably with conventional neural networks where the best systems currently require ∼10 mJ/inference, with projections to ∼100 μJ/inference. , …”

Section: Resultsmentioning

confidence: 99%

Co-Design of Free-Space Metasurface Optical Neuromorphic Classifiers for High Performance

et al. 2021

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Classification of features in a scene typically requires conversion of the incoming photonic field into the electronic domain. Recently, an alternative approach has emerged whereby passive structured materials can perform classification tasks by directly using freespace propagation and diffraction of light. In this manuscript, we present a theoretical and computational study of such systems and establish the basic features that govern their performance. We show that system architecture, material structure, and input light field are intertwined and need to be co-designed to maximize classification accuracy. Our simulations show that a single layer metasurface can achieve classification accuracy better than conventional linear classifiers, with an order of magnitude fewer diffractive features than previously reported. from multiple layer designs. Finally, we show a trade-off between the number of apertures and fabrication noise.

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Section: Resultsmentioning

confidence: 99%

Co-Design of Free-Space Metasurface Optical Neuromorphic Classifiers for High Performance

et al. 2021

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“…To compare the performance of the proposed circuit with other reported circuits, all the targeted circuit topologies including the conventional double-tail and the circuits reported in [1,11,26] as well as the proposed comparator in this paper are simulated in CNTFET technology under the same simulation conditions, (F ClK = 6 GHz, V DD = 1 V, ΔVin = 0.3 mV and C L = 5 fF). The simulation results are summarised in Table 2 and shown in Figure 10.…”

Section: R On3ð4þ C F Nðf Pþ Dt ð5þmentioning

confidence: 99%

“…In Table 1, a common-mode voltage of 0.7 V is selected for both the proposed comparator and the circuit reported in [1], since they both employ N-Type transistors as the input differential pair in their pre-amplifier stage. Moreover, a common-mode voltage of 0.3 V is applied for the structures reported in [11,26], since they employ a P-Type transistor input differential pair in their pre-amplifier stage. Therefore, the conditions are considered the same for all the comparator circuits.…”

Section: R On3ð4þ C F Nðf Pþ Dt ð5þmentioning

confidence: 99%

“…In [26], a hybrid double-tail comparator is proposed to reach the high-speed and low-power performances. Similar to the structure discussed in [1], the pre-amplifier stage includes a positive feedback structure.…”

Section: Recently Reported Double-tail Dynamic Comparator Designsmentioning

confidence: 99%

“…In [1,[8][9][10][11][12][13][14] and [26][27][28], the positive feedback circuit has been added to the core body of the pre-amplifier stage to significantly reduce the comparator response time (delay). However, the positive feedback circuit itself increases both the power consumption as well as the input-referred noise [1].…”

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An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Mahmoodian

Dolatshahi

Zanjani

et al. 2022

IET Circuits, Devices & Syst

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In this paper, a latch‐based energy‐efficient dynamic comparator is presented in Carbon Nanotube Field Effect Transistor (CNTFET) technology. The proposed comparator consists of two main stages: pre‐amplifier and latch. The latch stage is designed for the main purpose of low‐power consumption and high‐speed performances. The proposed speed‐up technique for the latch structure controls the threshold voltage (Vth) of the cross‐coupled inverters. So, the delay of the latch stage decreases and consequently, the overall delay of the comparator circuit is also reduced up to 19.4% while the maximum speed performance of the proposed comparator increases by 54% compared to the conventional double‐tail dynamic comparator. Additionally, the use of the proposed distinctive structure for the tail transistors in the latch stage, leads to more than 11% reduction in the energy per conversion of the proposed circuit compared to the conventional double‐tail dynamic comparator. To verify the circuit performances, the comparator circuit is simulated in HSPICE using 32 nm CNTFET Stanford model technology parameters. The simulation results show that the proposed comparator with the proposed speed‐up approach can operate up to 14.2 GHz with a sensitivity of 30 μV at the supply voltage of 1 V, while consumes only 42.38 μW of power. Therefore, the proposed comparator can be used in high‐resolution (up to 12 bit) and high‐speed low‐power analogue‐to‐digital converter applications. Moreover, the effects of the non‐ideal fabrication process (including the pitch and the threshold voltage variations), supply voltage and temperature variations are investigated in this work. Monte‐Carlo analysis shows that the standard deviation of the offset voltage is approximately 1.24 mV. Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.

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Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs

Dubey

Varshney

Kumar

et al. 2020

Lecture Notes in Electrical Engineering

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An energy-efficient high-speed CMOS hybrid comparator with reduced delay time in 40-nm CMOS process

Cited by 29 publications

References 28 publications

Co-Design of Free-Space Metasurface Optical Neuromorphic Classifiers for High Performance

Co-Design of Free-Space Metasurface Optical Neuromorphic Classifiers for High Performance

An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications

Design and Performance of High-Speed CMOS Double-Tail Dynamic Comparator Suitable for Mixed-Signal ICs

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