A High-Speed Low-Offset Double Tail Dynamic Comparator for Low-Power Applications
Reena George,
Nagesh Ch
Abstract:This paper presents a double tail dynamic comparator (DTDC) to obtain the high speed, low-power and low-offset voltage. In the proposed design, a regenerative latch is activated more quickly and it uses the lowest amount of power with an addition of two PMOS switching transistors MR4 and MR5 to the latch stage. The design and simulations are carried out in 90 nm CMOS technology with the supply voltage of 0.8 V having the clock frequency of 1 GHz. The simulation results confirm that the power consumption and of… Show more
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