A novel online offset-cancellation mechanism in a low-power 6-bit 2GS/s flash-ADC

Amini, Abdollah; Baradaranrezaeii, Ali; Hassanzadazar, Mina

doi:10.1007/s10470-018-1375-2

Cited by 8 publications

(2 citation statements)

References 10 publications

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“…As compared to resistive installation the capacitive interpolation consumes low power, provides verifiable track-and-hold operation, and has no boundary impacts, resulting in an effective drive simple conversion interface. Since the circuit size is not negligible, RF design approaches that use EMF and simulation links design are needed for the highest conversion speed using advanced CMOS techniques [15]. As a result, this circuit needs careful attention to its feature and bandwidth for sampling the analogue signal in track and hold buffers, and Master-Slave (MS) flipflops are used in comparators, but 10-GHz frequency circuits are extremely difficult to build.…”

Section: Related Workmentioning

confidence: 99%

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Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

Prathiba¹,

Santhi²

2022

Intelligent Automation &Amp; Soft Computing

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High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes a four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A low-power Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and a compact Binary Encoder (BE) are all part of the presented structure. A clock network in the comparator circuit reduces skew and jitters, while an ABF logic circuit detects and corrects fourth order bubble faults detected from thermometer code, and then the BE transforms the bubble free code into binary code. A Tanner EDA with 250-nm Technology is used to implement the C-FADC. The proposed design achieves ENOB of 3.56, uses 3.24 mW of power, and has a FOM of 0.274pJ/conv.-step at an input frequency of 85 MHz. The suggested C-FADC has differential and integral nonlinearities of ±0.65 LSB and +0.45/-0.5 LSB, respectively.

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Section: Related Workmentioning

confidence: 99%

“…It is demonstrated that in FADC architectures, the arranged Clocked Flash ADC can achieve incredible one-of-a-kind execution and a superior balance between Speed, Power, FOM, and VRB. In comparison to the references[1,2,4,7,8,10,11,14,15,19,20,22], the exhibited work uses low power 3.24 mW, and the Figure of Merit (FOM) is lower than the authors[4,8,10,14].…”

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confidence: 97%