A 10-bit 50MS/s pipeline ADC based on kickback-rejected comparators improved for small-amplitude inputs

Abstract

A 10-bit pipeline analog-to-digital converter is presented with the ability of converting small input peak-topeak voltages of around 100mvolts. Two-Stage comparators in flash structure are cautiously scheduled for both preamplification and latch operations, applying a simple switching strategy to reduce the coupling noise effect of transferring digital signals into analog sections. Namely, the digital signal which is used to schedule pre-amplification and latch operations is shared for all comparators such that be transferred out of the analog section in geometrical floorplanning. The first stage is also modified to reduce kickback noise effect of latch stage on analog inputs. Simulation results confirm the SNDR and SFDR of around 60.9dB and 71.5dB for 1.5MHz input frequency at 32MS/s sampling rate, respectively, when the peak-to-peak of input signal is 100mvolts. These values are reduced to 59.9dB and 70.6dB at near nyquist input frequency, around 15.5MHz. Also, at 50MS/s sampling rate, SNDR and SFDR are obtained around 57dB and 66.6dB at near nyquist input frequency of 24.2MHz.