Improved on-chip router analytical power and area modeling

Kahng,; Lin, Bin; Samadi,

doi:10.1109/aspdac.2010.5419887

Cited by 22 publications

(16 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Finally, the simulation takes place and the values obtained from the network simulator are used by the power-area estimator together with the power-energy-area expressions described in Section IV-A. Tools: A modified version of Booksim [21] was used for cycle accurate micro-architecture level network simulation and Orion3 [22,23] for the router-link power-area estimation. Orion was further modified to incorporate with our custom model (described in Section IV-B) for link pipelining.…”

Section: B Experimental Infrastructurementioning

confidence: 99%

Design space exploration for fair resource-allocated NoC architectures

Psathakis

Papaefstathiou

Katevenis

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

View full text Add to dashboard Cite

Networks-on-chip are integral parts of modern chips and designers explore the architectural design space to optimize both performance and energy-efficiency. Architectural choices for modern NoCs include: (i) partitioning using multiple subnetworks (P), (ii) concentration (C), and (iii) express physical links (X). Previous efforts do not adequately cover the design space while the range of assumptions vary significantly, rendering direct comparisons between different configurations impossible.This work expands the NoC design space and overcomes previous shortcomings by exploring the impact of architectural choices (P, C, X) separately and combinatorially on a 2D mesh. We generate all possible NoC configurations for large systems (64 and 256 nodes) and compare performance, energy, and area when the configurations utilize equal resources. First, we equalize the bisection wire count and analyze the impact of P, C, and X on NoC buffer space using analytical formulas. Then, we distribute an equal amount of buffer space in each NoC configuration by adjusting the respective router micro-architecture. Our results indicate that, with equal resources, none of the configurations exceeds the performance of the baseline 2D mesh. Moreover, we find that as node count increases to hundreds, the exclusive use of express physical links with an interval of 2 is the best approach in terms of energy and area. Furthermore, we observe that partitioning under equal buffer space and bisection bandwidth results in increased energy and area.

show abstract

Section: B Experimental Infrastructurementioning

confidence: 99%

Design space exploration for fair resource-allocated NoC architectures

Psathakis

Papaefstathiou

Katevenis

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

View full text Add to dashboard Cite

show abstract

“…The use of machine learning techniques has recently generated great interest with such techniques applied in design research problems [7,11,12]. The basic idea of machine learning is to use the actual implementation of some process or phenomenon to train or guide a model and then use it to predict the same metric for new input data.…”

Section: A Machine Learning In Vlsimentioning

confidence: 99%

“…Existing techniques of on-chip variation modeling during physical design are well established for 2D ICs but they need to be developed for 3D IC designs. Use of machine learning-based modeling techniques has recently gained a lot of interest [7]. In this work, we explore non-linear regression as the machine learning techniques to develop a fast accurate variation model for two-tier 3D ICs along with 2D ICs.…”

Section: Introductionmentioning

confidence: 99%

Machine Learning Based Variation Modeling and Optimization for 3D ICs

Samal¹,

Lim²

2016

Journal of information and communication convergence engineerin

View full text Add to dashboard Cite

Three-dimensional integrated circuits (3D ICs) experience die-to-die variations in addition to the already challenging withindie variations. This adds an additional design complexity and makes variation estimation and full-chip optimization even more challenging. In this paper, we show that the industry standard on-chip variation (AOCV) tables cannot be applied directly to 3D paths that are spanning multiple dies. We develop a new machine learning-based model and methodology for an accurate variation estimation of logic paths in 3D designs. Our model makes use of key parameters extracted from existing GDSII 3D IC design and sign-off simulation database. Thus, it requires no runtime overhead when compared to AOCV analysis while achieving an average accuracy of 90% in variation evaluation. By using our model in a full-chip variation-aware 3D IC physical design flow, we obtain up to 16% improvement in critical path delay under variations, which is verified with detailed Monte Carlo simulations.

show abstract

“…Dubois et al [8] use KG to estimate area of network-on-chip (NoC) routers. Kahng et al [16] use MARS to estimate NoC router area and power. Goel et al [9] demonstrate that weighted surrogate modeling is significantly more accurate than individual surrogate models.…”

Section: Related Workmentioning

confidence: 99%

High-dimensional metamodeling for prediction of clock tree synthesis outcomes

Kahng

Lin

Nath

2013

2013 ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP)

Self Cite

View full text Add to dashboard Cite

Abstract-Clock tree synthesis (CTS) is a key aspect of on-chip interconnect, and major consumer of IC power and physical design resources. In modern sub-28nm tools and flows, it has become exceptionally difficult to satisfy skew, insertion delay and transition time constraints within power and area budgets, in part because commercial tools (with their many knobs) have become highly complex. This complexity, along with the complicated structure of real-world CTS instances (hierarchy, dividers, etc.) and floorplan contexts (aspect ratios, obstacles, etc.) make it very difficult to predict skew, power and other important metrics of CTS outcomes. In this work, we study CTS estimation in the high-dimensional parameter space of instance constraints and floorplan contexts. Using two leading commercial CTS tools as our testbed, we develop predictors, classifiers and "field of use" characterizations that can enable IC design teams to achieve required CTS solution quality through understanding of appropriate parameter subspaces. Our hierarchical hybrid surrogate modeling approach mitigates challenges of parameter multicollinearity in high dimensions. It achieves, e.g., worst-case estimation errors of 13% in contrast to 30% errors in [17]. We demonstrate use of a 94%-accurate "oracle" classifier and estimation models to predictably achieve CTS outcomes that meet specified constraints and target metrics.

show abstract

Improved on-chip router analytical power and area modeling

Cited by 22 publications

References 18 publications

Design space exploration for fair resource-allocated NoC architectures

Design space exploration for fair resource-allocated NoC architectures

Machine Learning Based Variation Modeling and Optimization for 3D ICs

High-dimensional metamodeling for prediction of clock tree synthesis outcomes

Contact Info

Product

Resources

About