Abstract:Networks-on-chip are integral parts of modern chips and designers explore the architectural design space to optimize both performance and energy-efficiency. Architectural choices for modern NoCs include: (i) partitioning using multiple subnetworks (P), (ii) concentration (C), and (iii) express physical links (X). Previous efforts do not adequately cover the design space while the range of assumptions vary significantly, rendering direct comparisons between different configurations impossible.This work expands … Show more
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