High-dimensional metamodeling for prediction of clock tree synthesis outcomes

Abstract

Abstract-Clock tree synthesis (CTS) is a key aspect of on-chip interconnect, and major consumer of IC power and physical design resources. In modern sub-28nm tools and flows, it has become exceptionally difficult to satisfy skew, insertion delay and transition time constraints within power and area budgets, in part because commercial tools (with their many knobs) have become highly complex. This complexity, along with the complicated structure of real-world CTS instances (hierarchy, dividers, etc.) and floorplan contexts (aspect ratios, obstacles, etc.) make it very difficult to predict skew, power and other important metrics of CTS outcomes. In this work, we study CTS estimation in the high-dimensional parameter space of instance constraints and floorplan contexts. Using two leading commercial CTS tools as our testbed, we develop predictors, classifiers and "field of use" characterizations that can enable IC design teams to achieve required CTS solution quality through understanding of appropriate parameter subspaces. Our hierarchical hybrid surrogate modeling approach mitigates challenges of parameter multicollinearity in high dimensions. It achieves, e.g., worst-case estimation errors of 13% in contrast to 30% errors in [17]. We demonstrate use of a 94%-accurate "oracle" classifier and estimation models to predictably achieve CTS outcomes that meet specified constraints and target metrics.

OCV-aware top-level clock tree optimization

“…Kahng et al [11] improve CTS testcases by adding CLCs (Figures 3(a) and 3(b) in [11]) but two key elements ignored: (1) logic between FF groups and hence critical paths between FF groups; and (2) multiple clock sources. The CTS problem becomes difficult when synchronous and asynchronous clocks need to be balanced across multiple FF groups.…”

“…The CTS problem becomes difficult when synchronous and asynchronous clocks need to be balanced across multiple FF groups. We improve over [11] by (1) adding combinational logic with varying number of stages between FF groups, (2) adding multiple synchronous and asynchronous clocks, (3) using CLCs at different hierarchies to make the clock balancing problem very complex, (4) creating multiple top-level clock hierarchies, and (5) performing CTS with MCMM and OCV constraints. Figures 6(a)-(f) show the six testcases T1-T6 used in our experiments.…”

“…We spend most of the time to extract timing information and to formulate the LP. 11 CLC placement, buffer insertion, legalization and routing only take 10 minutes in total because there are not many cells in the top-level clock tree. The total runtime is 135 minutes on average.…”

“…The results in Rows 15-16 shows that our optimization flow reduces the total wirelength by 38% to 51% across all six testcases. The improvements are smaller as compared to the post-CTS stage because the total wirelength of the initial and optimized clock trees 11 Solving the LP takes less than 30 seconds. both increase at the post-routing stage due to wiring of the signal nets.…”

How Deep Learning Can Drive Physical Synthesis Towards More Predictable Legalization

“…The high flexibility provided by machine learning (ML) models allows their use to predict the outcome of physical design algorithms. They have been employed so far to help choose between different clock tree synthesis algorithms [11], to fix miscorrelations between different timing engines [7], and to identify detailed routing violations during the placement stage [2,17,19]. The benefits of ML models come from their ability to improve the quality of physical design algorithms by predicting information that would otherwise be too costly to evaluate during execution.…”