OCV-aware top-level clock tree optimization

Chan, Theodore; Han, Kwangsoo; Kahng, Andrew B.; Lee, Jae-Gon; Nath, S.

doi:10.1145/2591513.2591541

Cited by 16 publications

(5 citation statements)

References 18 publications

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“…Shelar [16] proposed a clustering method to reduce the number of buffers and power consumption. Chan et al [17] proposed a linear programming methodology to minimize power consumption, wire length, and timing slew simultaneously. Lin et al [18] proposed an activity-driven clock tree design methodology, including a new tree structure and a corresponding design flow.…”

Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

et al. 2023

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In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. The clock tree architecture has a shorter wire length and better power consumption, but it is more difficult to achieve timing closure with it. On the other hand, clock mesh architecture is easier to satisfy the clock skew constraint, but it usually has much more power consumption. Therefore, a hybrid clock network architecture that combines both the clock tree and clock mesh seems to be a promising solution. In a normal hybrid mesh/tree structure, a driving buffer is placed in the intersection of mesh lines. In this paper, we propose a novel cross-mesh architecture, and we distribute the buffers to balance the overall switching capacitance, reducing the number of registers connected to a subtree, and the load capacitance of a buffer. With the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating, register clustering, and load balancing techniques to optimize clock skew and load capacitance simultaneously. The proposed methodology has four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our cross-mesh architecture has high tolerance for process variation, and is robust in all the operation modes. Comparing it to the uniform mesh architecture, our methodology and algorithms reduce 28.9% of load capacitance and 80.4% of clock skew on average. Compared to the non-uniform mesh architecture, we also reduce capacitance by 22.4% and skew by 76.7% on average. This illustrates that we can obtain a feasible solution effectively and improve both power consumption and clock skew simultaneously.

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Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

et al. 2023

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“…Research [14] proposed a clustering method to reduce the number of buffers and power consumption. Research [15] proposed a linear programming methodology to minimize power consumption, wire length, and timing slew simultaneously. Research [16] proposed an activitydriven clock tree design methodology, including a new tree structure and a corresponding design flow.…”

Section: Clock Treementioning

confidence: 99%

Cross-Mesh Clock Network Synthesis

Cheng¹,

Yeh²,

Kao³

et al. 2023

Preprint

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In the clock network design, the trade-off between power consumption and timing closure is an important and difficult issue. To achieve this target, a hybrid clock network architecture that combines both clock tree and clock mesh seems to be a promising solution. In this paper, we propose a novel clock mesh architecture – cross-mesh, with the average dispersion of the overall driving force, our methodology creates small non-zero skew clock trees. In addition, we integrate clock gating and register clustering techniques to further reduce dynamic power consumption. The proposed algorithms have four stages: cross-mesh planning, register clustering, mesh line connecting, and load balancing. Experimental results show that our methodology and algorithms get feasible solution effectively and improve both power consumption and clock skew simultaneously.

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“…1 We also perform a novel stress test of 3DPE by verifying that the model cannot produce unreasonable values of estimated 3D power benefit. While practitioners have struggled with a gap between theoretical limits of 3DIC benefit and observed benefits, our model stress test provides some encouragement in the form of model parameter combinations that suggest potential large 3DIC power benefits.…”

Section: Introductionmentioning

confidence: 99%

“…In our 28nm FDSOI libraries, the size of the largest cell is 4.4µm 2 . The inter-buffer distance is ∼120-150µm[1]. The max transition is 375ps and the max fanout is 20.…”

mentioning

confidence: 99%

3DIC benefit estimation and implementation guidance from 2DIC implementation

Chan

Nath

Kahng

et al. 2015

Proceedings of the 52nd Annual Design Automation Conference

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Quantification of three-dimensional integrated circuit (3DIC) benefits over corresponding 2DIC implementation for arbitrary designs remains a critical open problem, largely due to nonexistence of any "golden" 3DIC flow. Actual design and implementation parameters and constraints affect 2DIC and 3DIC final metrics (power, slack, etc.) in highly non-monotonic ways that are difficult for engineers to comprehend and predict. We propose a novel machine learningbased methodology to estimate 3DIC power benefit (i.e., percentage power reduction) based on corresponding golden 2DIC implementation parameters. The resulting 3D Power Estimation (3DPE) models achieve small prediction errors that are bounded by construction. We are the first to perform a novel stress test of our predictive models across a wide range of implementation and design-space parameters. Further, we explore model-guided implementation of designs in 3D to achieve minimum power: that is, our models recommend a mostpromising set of implementation parameters and constraints, and also provide a priori estimates of 3D power benefits, based on a given design's post-synthesis and 2D implementation parameters. We achieve ≤10% error in power benefit prediction across various 3DIC designs.

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OCV-aware top-level clock tree optimization

Cited by 16 publications

References 18 publications

Cross-Mesh Clock Network Synthesis

Cross-Mesh Clock Network Synthesis

Cross-Mesh Clock Network Synthesis

3DIC benefit estimation and implementation guidance from 2DIC implementation

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