Improved film growth and flatband voltage control of ALD HfO/sub 2/ and Hf-Al-O with n/sup +/ poly-Si gates using chemical oxides and optimized post-annealing

Wilk, G. D.; Green, M.L.; Ho, M.-Y.; Busch, B.; Sorsch, T.; Klemens, F.; Brijs, Bert; Dover, R. B. van; Kornblit, A.; Gustafsson, T.; Garfunkel, Eric; Hillenius, S.J.; Monroe, Don; Kalavade, P.; Hergenrother, J. M.

doi:10.1109/vlsit.2002.1015401

Cited by 23 publications

(21 citation statements)

References 1 publication

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“…This agrees with results previously reported that aluminates with -poly gate show considerable negative fixed charge, 6-8E12 cm , while HfO film showing much smaller fixed charges cm [2], [5]. showing thermal stability up to 800 C for 20% Al and 900 C for 38% Al, respectively.…”

Section: Resultssupporting

confidence: 92%

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Bae¹,

Lee²,

Clark³

et al. 2003

IEEE Electron Device Lett.

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Thermally stable, high-quality ultrathin (EOT = 13 A) CVD HfAlO gate dielectrics with poly-Si gate electrode have been investigated for the first time. Results demonstrate that while in situ doping with Al significantly increases the crystallization temperature of HfO 2 up to 900 C and improves its thermal stability, it also introduces negative fixed oxide charges due to Al accumulation at the HfAlO-Si interface, resulting in mobility degradation. The effects of Al concentration on crystallization temperature, fixed oxide charge density, and mobility degradation in HfAlO have been characterized and correlated.

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Section: Resultssupporting

confidence: 92%

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Bae¹,

Lee²,

Clark³

et al. 2003

IEEE Electron Device Lett.

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“…Incorporation of aluminum into HfO 2 by forming (HfO 2 ) 1-x (Al 2 O 3 ) x films [1][2][5][6][7][8][9][10][11][12] or HfO 2 /Al 2 O 3 bi-layers [2,[13][14] was reported to be promising for high-κ on silicon and high mobility substrates. The addition of Al into HfO 2 can downscale the equivalent oxide thickness (EOT), reduces the gate leakage current density (J g ) and provides a better thermal stability on Si [1][2][3][4][5][6][7][8][9][10][11][12][13][14]. However, Al concentration in the dielectrics needs to be maintained to an extremely low level for highly scaled transistors.…”

mentioning

confidence: 99%

Reliability of HfAlO<inf>x</inf> in multi layered gate stack

Bhuyian

Misra

2015

2015 IEEE International Reliability Physics Symposium

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This work has demonstrated a high quality HfO 2 based gate stack by depositing HfAlO x along with HfO 2 in a layered structure. In order to get multifold enhancement of the gate stack quality both Al percentage and distribution were observed by varying the HfAlO x layer thickness and it was found that < 2% Al/(Al+Hf)% incorporation can result in up to 18% reduction in average EOT along with up to 41% reduction in gate leakage current as compared to the dielectric with no Al content. On the other hand, excess Al presence in the interfacial layer moderately increased the interface state density (D it ). When devices were stressed in the gate injection mode at a constant voltage stress, dielectrics with Al/(Hf+Al)% < 2% showed resistance to stress induced flat-band voltage shift (ΔV FB ), and stress induced leakage current (SILC). The time dependent dielectric breakdown (TDDB) characteristics showed a higher charge to breakdown and an increase in the extracted Weibull slope ( ) that further confirms an enhanced dielectric reliability for devices with < 2% Al/(Al+Hf)%. Keywords-Equivalent oxide thickness (EOT), HfAlO x , interface state density (D it ), stress induced flat-band voltage shift (ΔVFB), stress induced leakage current (SILC), time dependent dielectric breakdown (TDDB).

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“…The low EOT can be attributed to the t-HfO 2 formed by in situ high-k/IL process. In addition, the surface uniformity of high-k dielectric can be improved by OH bond on the IL [26], since the OH or H bond could reduce the defect in IL layer. For sample with an H 2 O 2 solution treatment at high temperature, the EOT value of 0.61 nm is also low and the J g of 1 A/cm 2 is acceptable.…”

Section: Methodsmentioning

confidence: 99%

An Ultralow EOT Ge MOS Device With Tetragonal HfO2 and High Quality Hf<italic>x</italic>Ge<italic>y</italic>O Interfacial Layer

Chang‐Liao

Liu

et al. 2014

IEEE Trans. Electron Devices

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A Ge MOS device with an ultralow equivalent oxide thickness of ∼0.5 nm and acceptable leakage current of 0.5 A/cm 2 is presented in this paper. The superior characteristics can be attributed to a tetragonal HfO 2 with a higher k value (k ∼ 31) and comparable bandgap. In addition, a Ge MOS device with tetragonal phase HfO 2 (t-HfO 2 ) also shows a lower leakage current and better thermal stability. The mechanisms for t-HfO 2 formation may be explained by the little Ge diffusion from Ge substrate and oxygen deficiency, which are obtained by in situ interfacial layer (IL) formation and high-k processes. The IL with k ∼ 13 can be formed by in situ H 2 O plasma treatment. Moreover, a Ge MOS device with the IL grown by H 2 O plasma shows smaller interface trap density and hysteresis effects due to a high composition of Ge +4 .

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Improved film growth and flatband voltage control of ALD HfO/sub 2/ and Hf-Al-O with n/sup +/ poly-Si gates using chemical oxides and optimized post-annealing

Cited by 23 publications

References 1 publication

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

MOS characteristics of ultrathin CVD HfAlO gate dielectrics

Reliability of HfAlO<inf>x</inf> in multi layered gate stack

An Ultralow EOT Ge MOS Device With Tetragonal HfO<sub>2</sub> and High Quality Hf<sub><italic>x</italic></sub>Ge<sub><italic>y</italic></sub>O Interfacial Layer

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