Implications of Ageing Through Power Cycling on the Short-Circuit Robustness of 1.2-kV SiC mosfets

Abstract

In this paper, the reliability performance of 1.2-kV SiC power MOSFET modules is investigated through the combination of both accelerated power cycling tests and short circuit tests. The short-circuit robustness of SiC MOSFETs is investigated after stressing the dies under power cycling tests. In this way, the implications of different levels of degradation on the short circuit capability can be better understood. During the power cycling tests, some electrical parameters, either related to the package or the die, may experience variations as a consequence of the device ageing (e.g., increase in bond wire resistance and increase in gate leakage current). The effect of these parameter variations on the short-circuit withstanding capability of SiC MOSFETs is investigated for the first time in this work. The proposed method helps to understand which degradation effects under normal operation have a major implication on the short-circuit robustness, which gives a more realistic information about the root cause of the failures observed in the field.

Power Electronics Reliability: State of the Art and Outlook

“…Much effort has been made in the short-circuit testing [27][28][29][30][31][32][33], [34] of SiC MOSFETs and its protection in power converter design [34][35][36][37][38]. In [27], comparative testing of two types of 1.2 kV/24 A SiC MOSFETs with Si MOSFET is given.…”

“…This shows that with the increase of case temperature, the number of repetitive shortcircuit to failure increases because the energy dissipated during the short-circuit operation decreases with the increase of case temperature due to the negative temperature coefficient of the MOSFETs. The impact of degradation on the short-circuit withstanding capability of a 1.2 kV SiC MOSFET module has been investigated [33] based on comparisons between new samples and aged samples from power cycling test. This study shows that the gate-oxide degradation has a more significant impact on the short-circuit withstand time than the packaginglevel degradation.…”

Effect of short-circuit degradation on the remaining useful lifetime of SiC MOSFETs and its failure analysis

“…The number of cycles to failure (Nf1) is recorded when either device first shows an extremely high VDS,on or open circuit failure mode to mitigate the impact of the deviation. Then the number of cycles equal to 10%•Nf1 is selected as the point to introduce short-circuit events since the devices remain consistent characteristics at the early of the test and the impact of power cycling ageing on the shortcircuit performance is negligible [7]. Thereafter, another three sets of power cycling tests are run.…”

(Invited) Ruggedness of SiC and GaN Power Transistors in Switching Based Tests

“…The final traditional ruggedness experiments in Figure 1 are more related to device operation outside of the SOA. The UIS tests (1,2,18,19) and Short Circuit tests (20,21), generate stresses on both the intrinsic and extrinsic levels. UIS tests push the device into an avalanche conduction state (if the device has avalanching capabilities), while short circuit tests push the device out of the linear conduction region and into the saturation conduction region.…”