Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology

Puttaswamy, Kiran; Loh, Gabriel H.

doi:10.1109/isvlsi.2006.56

Cited by 21 publications

(14 citation statements)

References 18 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Two functional blocks connected by a global wire in a planar IC can instead be stacked to drastically reduce the wire lengths. Wire-dominated functional blocks such as caches and register files can be stacked on top of themselves to reduce intra-block wiring [2,3,4]. Reducing the amount of wire can also have a significant impact on power consumption [5].…”

Section: Introductionmentioning

confidence: 99%

Thermal analysis of a 3D die-stacked high-performance microprocessor

Puttaswamy

Loh

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

132

View full text Add to dashboard Cite

3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional planar ICs, 3D ICs have shorter latencies as well as lower power consumption, due to shorter wires. The benefits of 3D ICs increase as we stack more die, due to successive reductions in wire lengths. However, as we stack more die, the power density increases due to increasing proximity of active (heat generating) devices, thus causing the temperatures to increase. Also, the topmost die on the 3D stack are located further from the heat sink and experience a longer heat dissipation path. Prior research has already identified thermal management as a critical issue in 3D technology. In this paper, we evaluate the thermal impact of building high-performance microprocessors in 3D. We estimate the temperatures of a planar IC based on the Alpha 21364 processor as well as 2-die and 4-die 3D implementations of the same. We show that, compared to the planar IC, the 2-die implementation and 4-die implementation increase the maximum temperature by 17 Kelvin and 33 Kelvin, respectively.

show abstract

Section: Introductionmentioning

confidence: 99%

Thermal analysis of a 3D die-stacked high-performance microprocessor

Puttaswamy

Loh

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

132

View full text Add to dashboard Cite

show abstract

“…Fig. 5 shows the conventional three ports (i.e., two reads and one write port) SRAM cell used in memory cell of register file [13,15,31,38,6]. The cell is composed of two inverters and three pairs of pass transistors.…”

Section: Modified Register File Structure For Reducing Dynamic Powermentioning

confidence: 99%

Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana

Khameneh

Goudarzi

2015

Microprocessors and Microsystems

View full text Add to dashboard Cite

“…Two functional blocks connected by a long global route in a planar implementation can instead be vertically stacked to drastically reduce the communication distance by routing in the third dimension. Wire-dominated functional unit blocks can be folded on top of themselves to reduce the effects of intra-block wiring [19,23,24]. Reducing the amount of wire can also have a significant impact on power consumption [25].…”

Section: D Integration Technologymentioning

confidence: 99%

Dynamic instruction schedulers in a 3-dimensional integration technology

Puttaswamy

Loh

2006

Proceedings of the 16th ACM Great Lakes Symposium on VLSI

View full text Add to dashboard Cite

We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the critical path latency of a conventional dynamic scheduler is greatly affected by wire delay, we propose 3D-integrated scheduler designs by partitioning a conventional scheduler across multiple vertically-stacked die. The die-stacked organization reduces the lengths of critical wires thus reducing both latency and energy. Our simulation results show that a 20-entry (60-entry) instruction scheduler implemented in a 2-die stack achieves a 9% (15%) reduction in latency with simultaneous energy reduction as compared to a conventional planar design. The benefits are even larger when the instruction scheduler is implemented on a 4-die stack, with the corresponding latency reductions being 12% (22%).

show abstract

Implementing Register Files for High-Performance Microprocessors in a Die-Stacked (3D) Technology

Cited by 21 publications

References 18 publications

Thermal analysis of a 3D die-stacked high-performance microprocessor

Thermal analysis of a 3D die-stacked high-performance microprocessor

Dynamically adaptive register file architecture for energy reduction in embedded processors

Dynamic instruction schedulers in a 3-dimensional integration technology

Contact Info

Product

Resources

About