Thermal analysis of a 3D die-stacked high-performance microprocessor

Abstract

3-dimensional integrated circuit (3D IC) technology places circuit blocks in the vertical dimension in addition to the conventional horizontal plane. Compared to conventional planar ICs, 3D ICs have shorter latencies as well as lower power consumption, due to shorter wires. The benefits of 3D ICs increase as we stack more die, due to successive reductions in wire lengths. However, as we stack more die, the power density increases due to increasing proximity of active (heat generating) devices, thus causing the temperatures to increase. Also, the topmost die on the 3D stack are located further from the heat sink and experience a longer heat dissipation path. Prior research has already identified thermal management as a critical issue in 3D technology. In this paper, we evaluate the thermal impact of building high-performance microprocessors in 3D. We estimate the temperatures of a planar IC based on the Alpha 21364 processor as well as 2-die and 4-die 3D implementations of the same. We show that, compared to the planar IC, the 2-die implementation and 4-die implementation increase the maximum temperature by 17 Kelvin and 33 Kelvin, respectively.

Oxidation Behavior of Copper at a Temperature below 300 °C and the Methodology for Passivation

“…As an example, the reported operating temperature of a central processing unit (CPU) can reach temperatures as high as 150 °C [8][9][10] . However, the oxidation behavior of copper at a temperature below 300 °C has received little attention.…”

“…Copper has been widely used as bonding wires or interconnects within many electronic components. Due to increasing component density and decreasing line width, the temperature within an electronic device may reach a temperature above 200 °C during operation [8][9][10] . In this study, the oxidation behavior of copper at 200 °C and 300 C in air is investigated.…”

Leveraging 3D Technology for Improved Reliability

“…The modeling parameters and thermal constants for each layer are as described in [2,26] and reproduced in Table 3. The heat sink is placed close to the bottom Table 3.…”

“…Many have focused on improving single-core performance and power [2,7,26,44]. Some of this attention has focused on implementing a cache in 3D [25,29,40], even in the context of a multi-core NUCA layout [16].…”

Design and Testing Strategies for Modular 3-D-Multiprocessor Systems Using Die-Level Through Silicon Via Technology

“…As illustrated in the analysis of a 3-D die-stacked microprocessor implementation by Puttaswamy et al [26], stacking identical multi-processor dies may obstruct heat transfer to the heat-sink resulting in a noticeable, yet limited, overall temperature increase of the system. In the extreme case of being unable to provide adequate heat dissipation for a 3-D die-stacked implementation, a number of solutions have been proposed.…”