Dynamic instruction schedulers in a 3-dimensional integration technology

Abstract

We present the design of high-performance and energy-efficient dynamic instruction schedulers in a 3-Dimensional integration technology. Based on a previous observation that the critical path latency of a conventional dynamic scheduler is greatly affected by wire delay, we propose 3D-integrated scheduler designs by partitioning a conventional scheduler across multiple vertically-stacked die. The die-stacked organization reduces the lengths of critical wires thus reducing both latency and energy. Our simulation results show that a 20-entry (60-entry) instruction scheduler implemented in a 2-die stack achieves a 9% (15%) reduction in latency with simultaneous energy reduction as compared to a conventional planar design. The benefits are even larger when the instruction scheduler is implemented on a 4-die stack, with the corresponding latency reductions being 12% (22%).

Dynamically heterogeneous cores through 3D resource pooling

“…A number of design approaches are possible and many have been proposed, from alternating cores and memory/cache [20,23], to folding a single pipeline across layers [27].…”

A new processor design based on 3D cache

“…Paul Reed et al [8] has studied the 3D integrated memory-processor and analyzed the sense amplifier. In [9], the author has studied a 3D stacked register file with cache in high-performance microprocessor architecture. However, most of these works simply consider the 3D memory and the processor to be different level or only stack entire memory with another memory to increase cache capacity, at the same time, there are few works focusing on overall performance of the 3D processor.…”

Fine grain 3D integration for microarchitecture design through cube packing exploration

“…An extensive amount of research has demonstrated the latency reduction through additional device layers [1,2,3,4,30], however most prior art on 3D [4,5,6] is restricted to stacking traditional 2D dies. Such stacking offers significant reduction in inter-block latency, whereas it does little to help intra-block wire latency.…”

“…Recent studies have provided block models for various architectural structures including 3D cache [9,12,13,14], register file [10,11] and instruction scheduler [30], along with 2D based placement tools such as [22]. However, these models are limited to folding blocks by wordlines or bitlines, and they do not explore further improvement from techniques such as port partitioning, which we shall discuss in Section 3.…”

“…Although multi-layer blocks can reduce the area, delay, and power consumption for each individual block [30,22], the best configuration for each single block may not lead to the best design for the entire multi-layered chip.…”