Dynamically adaptive register file architecture for energy reduction in embedded processors

Tavana, Mohammad Khavari; Khameneh, Saba Ahmadian; Goudarzi, Maziar

doi:10.1016/j.micpro.2015.01.005

Cited by 6 publications

(1 citation statement)

References 48 publications

(39 reference statements)

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“…The shrinking feature size of process technology has enhanced the potential performance of electronic devices, and the capacity of shift registers has increased significantly. Therefore, asking for less overhead integrated circuitry layout area [9][10][11][12] and less power consumption [9,11,[13][14][15][16][17][18][19][20][21][22][23][24][25][26] in the shift registers design then becomes more important with the capacity increasing [27].…”

Section: Introductionmentioning

confidence: 99%

A Novel Cross-Latch Shift Register Scheme for Low Power Applications

Kuo¹,

Sheu²,

Tsai³

et al. 2020

Applied Sciences

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The conventional shift register consists of master and slave (MS) latches with each latch receiving the data from the previous stage. Therefore, the same data are stored in two latches separately. It leads to consuming more electrical power and occupying more layout area, which is not satisfactory to most circuit designers. To solve this issue, a novel cross-latch shift register (CLSR) scheme is proposed. It significantly reduced the number of transistors needed for a 256-bit shifter register by 48.33% as compared with the conventional MS latch design. To further verify its functions, this CLSR was implemented by using TSMC 40 nm CMOS process standard technology. The simulation results reveal that the proposed CLSR reduced the average power consumption by 36%, cut the leakage power by 60.53%, and eliminated layout area by 34.76% at a supply voltage of 0.9 V with an operating frequency of 250 MHz, as compared with the MS latch.

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