Implementing Asynchronous Circuits on LUT Based FPGAs

Ho, Quoc Thai; Rigaud, Jean-Baptiste; Fesquet, Laurent; Renaudin, Marc; Rolland, Robin

doi:10.1007/3-540-46117-5_6

Cited by 57 publications

(21 citation statements)

References 3 publications

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“…However, the significant and variable routing delays of the signals within an FPGA can make it difficult to satisfy such constraints. Despite these issues, there have been attempts to implement asynchronous designs on synchronous FPGAs [100]; however, such approaches have been found to incur significant area and performance penalties [193]. Therefore, to enable more efficient asynchronous implementations, new FPGA architectures that incorporate asynchronous elements directly have been proposed [95,110,158,193,194,215].…”

Section: Asynchronous Fpgasmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

297

109

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Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade. A crucial part of their creation lies in their architecture, which governs the nature of their programmable logic functionality and their programmable interconnect. FPGA architecture has a dramatic effect on the quality of the final device's speed performance, area efficiency, and power consumption. This survey reviews the historical development of programmable logic devices, the fundamental programming technologies that the programmability is built on, and then describes the basic understandings gleaned from research on architectures. We include a survey of the key elements of modern commercial FPGA architecture, and look toward future trends in the field.

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Section: Asynchronous Fpgasmentioning

confidence: 99%

FPGA Architecture: Survey and Challenges

Kuon

Tessier

Rose

2008

FNT in Electronic Design Automation

297

109

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“…There has been some work that has developed hazard-free synthesis methods to map asynchronous logic to both standard FPGAs (e.g. [5], [22]) as well as FPGAs with support for asynchronous logic (e.g. [4]).…”

Section: A Quasi Delay Insensitive Logicmentioning

confidence: 99%

“…There has also been a some work on prototyping asynchronous logic using commercially available synchronous FPGAs (e.g. [5], [22]). …”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Asynchronous Logic

Manohar

2006

IEEE Custom Integrated Circuits Conference 2006

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Abstract-Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuitlevel flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

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“…It is based on the developing Muller gate library [16]. However, the area and speed penalty is rather high.…”

Section: Introductionmentioning

confidence: 99%

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints

Lemberski

Fišer

2010

2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools

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Abstract-Asynchronous circuit implementations operating under strong constraints (DIMS, Direct Logic, some of NCL gates, etc.) are attractive due to: 1) regularity; 2) combined implementation of the functional and completion detection logics, what simplifies the design process; 3) circuit output latency is based on the actual gate delays of the unbounded nature; 4) absence of additional synchronization chains (even of a local nature). However, the area and speed penalty is rather high. In contrast to the state-of-the-art approaches, where simple (NAND, NOR, etc.) 2-input gates are used, we propose a synthesis method based on complex nodes, i.e., nodes implementing any function of an arbitrary number of inputs. Synchronous synthesis procedures may be freely adopted for this purpose. Numerous experiments on standard benchmarks were performed and the efficiency of the proposed complex gate based method is clearly shown. DIMS and Direct Logic based asynchronous designs are considered in the paper.

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Implementing Asynchronous Circuits on LUT Based FPGAs

Cited by 57 publications

References 3 publications

FPGA Architecture: Survey and Challenges

FPGA Architecture: Survey and Challenges

Reconfigurable Asynchronous Logic

Area and Speed Oriented Implementations of Asynchronous Logic Operating under Strong Constraints

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