Reconfigurable Asynchronous Logic

Abstract

Abstract-Challenges in mapping asynchronous logic to a flexible substrate include developing a balance between circuitlevel flexibility, mapping complexity, and logic overhead. We have developed a reconfigurable dataflow architecture that addresses these challenges, and have also created the necessary synthesis flow required to map designs to the architecture. The architecture exploits some of the unique features of asynchronous logic, and attains a performance that significantly exceeds previous asynchronous FPGAs.

A split-foundry asynchronous FPGA

“…Our FPGA is based on the one described in [11] and [12]. It has an "island-style" architecture, as shown in Figure 1.…”

Architecture of an Asynchronous FPGA for Handshake-Component-Based Design

“…The LB of the conventional FPGA mainly consists of an LUT, an asynchronous register, an FPDR multiplexer and an FPDR demultiplexer [14]. In the conventional asynchronous FPGA, applications are designed combining seven building blocks [5]. Table 3 shows the comparison result of the cells of the proposed architecture and the conventional architecture.…”

“…Asynchronous FPGAs developed by Cornell University [4], [5], Achronix [6] and the University of Tokyo [7] employ finegrained pipelined architecture to achieve high throughput. References [8]- [10] propose asynchronous FPGA architecture focusing on low power consumption.…”

The Design of a Polymorphous Cognitive Agent Architecture (PCAA)

“…For a full discussion of the asynchronous programmable logic to be used for this design, see [Manohar06] and [Teifel04]. [Parunak04] have guided implementation studies of the hardware.…”