Implementation of elementary functions for logarithmic number systems

Johansson, Kenny; Gustafsson, Oscar; Wanhammar, Lars

doi:10.1049/iet-cdt:20070080

Cited by 32 publications

(17 citation statements)

References 9 publications

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“…ROM is used to store the coefficients. Research work has applied to digit-recurrence methods to perform the conversion which perform slow seed but save hardware costs [10,15,26]. 'Shift-and-Add' schemes have been used for suitable design tradeoffs [9,27].…”

Section: Literature Reviewmentioning

confidence: 99%

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An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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Multiplication is one of important arithmetic component for digital signal processing, neural network and image processing. But, it is well known fact that multiplier has most hardware consuming component out of all arithmetic components. Here, it is given a possible solution by using an efficient VLSI architecture of Mitchell's algorithm based Iterative Logarithmic Multiplier (ILM) with modified architecture of Leading One Detector (LOD) and seamless pipelined technique. The proposed work is based on the hardware minimization at the same error cost than of previously reported architectures. We use VHDL to design the existing and proposed Mitchell's algorithm based iterative logarithmic multiplier. Both multipliers design are evaluated with the Synopsys design compiler by using 90 nm CMOS technology and compared the results in terms of Data Arrival Time (DAT), area, power, Area Delay Product (ADP) and energy. The proposed Mitchell's based ILM gives 33.18 %, 39.03 % and 31.62 % less ADP, 25.08 %, 38.08 % and 46.72 % less energy for 8, 16, and 32 bits architecture respectively in comparison of the reported ILM. The importance of LODs and seamless pipeline has been shown in an efficient architecture of Mitchell's based ILM.

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Section: Literature Reviewmentioning

confidence: 99%

“…In 2006, V. Mahalingam et.al has given the Operand Decomposition (OD) as an independent approach to minimize the error [32]. In 2008, Johansson et al [26] have reported the approximation method. In 2010, Fu reported et al [18] have reported the polynomial approximation approach.…”

Section: Literature Reviewmentioning

confidence: 99%

An efficient architecture of iterative logarithm multiplier

Nandan¹,

Kanungo²,

Mahajan³

2018

IJET

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“…Several authors have proposed solutions to reduce complexity of awkward LNS operations. Mahalingam and Ranganathan improve Mitchell's Algorithm (MA) in terms of the accuracy of the logarithmic operations [7], while Johansson et al use a method based on sums of bit-products to implement the basic logarithmic functions [8]. Arnold et al suggest the use of co-transformations for the reduction of the look-up tables [9].…”

Section: Literature Reviewmentioning

confidence: 99%

Logarithmic Number System and Its Application in FIR Filter Design

Paliouras

2017

Embedded Systems Design With Special Arithmetic and Number Systems

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Data representation is an important parameter in the design of digital signal processors as it affects their performance and hardware complexity. Data representation influences the choice of algorithms and the hardware architecture, thus it has an impact on data storage requirements, processing performance, complexity, and power dissipation [1][2][3].The Logarithmic Number System (LNS) can be used to efficiently represent data in special-purpose processors. The efficiency of LNS stems from the properties of the logarithm exploited to reduce the basic arithmetic operations of multiplication, division, square roots, and squares to simple binary addition, subtraction, and right and left shifts, respectively [4]. Similarly, the computation of general roots and powers as well as of reciprocals are substantially simplified.Building on the reduced complexity of certain arithmetic operations, digital signal processor implementations can benefit from substantial architectural-level simplifications. Furthermore, beyond operation strength reduction, superior LNS dynamic range and numerical behavior, compared to conventional representations, are additional reasons that make LNS attractive. In order to fully utilize LNS potential, procedures are required to optimally define LNS design parameters and derive LNS solutions, matched to application specifications and requirements.

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“…Here partial sums are symbolically represented in the nodes of the graph while the edges are used to represent the shift amounts [28] Furthermore, different number representations have been used to take advantage of the inherent simplification of multiplication in them, like residue number system (RNS) [80][81][82][83][84] and LNS [85][86][87][88][89][90][91][92]. Most efforts towards utilizing LNS for digital filters have focused on either implementing the non-linear conversion to and from LNS, selecting the logarithm basis, or implementing the LNS addition and subtraction efficiently [92][93][94][95][96][97]. The finite word length filter design has not been considered, but instead relied on rounding the obtained coefficients to the nearest LNS number.…”

Section: Reduction In Multiplier Complexitymentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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Implementation of elementary functions for logarithmic number systems

Cited by 32 publications

References 9 publications

An efficient architecture of iterative logarithm multiplier

An efficient architecture of iterative logarithm multiplier

Logarithmic Number System and Its Application in FIR Filter Design

Techniques for Efficient Implementation of FIR and Particle Filtering

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