Techniques for Efficient Implementation of FIR and Particle Filtering

Abstract

Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

Injecting Reliable Radio Frequency Fingerprints Using Metasurface for The Internet of Things

“…1) FIR filter with window: Firstly, we can design a digital finite impulse response (FIR) filter, apply a suitable window function, then approximate the functions to make them implementable [27]. They can be implemented either by using a separate DSP chip [28] or by designing a dedicated system on a chip (SoC) [29] comprising of latches, multipliers, and adders.…”

“…a) Complexity analysis: Consider FIR filter with a Kaiser window that can alter the emitted carrier wave, which can supposedly act as an RFF. The choice of this specific method to analyze was considered primarily because the FIR method can be represented as integer math [27] and thus making them realizable with hardware compared to IIR filters. Secondly, a typical kaiser window [30] is applied here, which is appropriate for generating sharp peaks.…”

“…Finally, the computation of a Kaiser window, which has the complexity of O(N * log(N ), where N is the number of frequency samples points. The implementation of the first two steps can be performed either by DSP [27] or an SoC [29] as previously mentioned and the computation of custom window needs a numerical function generator (NFG) [31] unit. b) DSP implementation: Although there are very cheap DSP's available for as small a price as $2 [32], they have an idle power consumption of 0.15mW at 1.05V supply [32].…”

“…c) SoC implementation: The same filter implemented using SoC, however, would be faster as they can perform the operation in a single flow, but the complexity of the 3 stages are tough to be designed in a single chip without significant approximations [27], as they rely on implementing the operation with only latches, multipliers, and adders. Also, the power consumption of such a filter to of size N = 16 is estimated to be 28.7mW for low throughput applications [34], thus making them unaffordable for IoT devices.…”