Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder

Abstract

Architecture for Dynamically Reconfigurable Embedded Systems (ADRES) is a templatized coarsegrained reconfigurable processor architecture. It targets at embedded applications which demand highperformance, low-power and high-level language programmability. Compared with typical very long instruction word-based digital signal processor, ADRES can exploit higher parallelism by using more scalable hardware with support of novel compilation techniques. We developed a complete tool-chain, including compiler, simulator and HDL generator. This paper describes the design case of a media processor targeting at H.264 decoder and other video tasks based on the ADRES template. The whole processor design, hardware implementaiton and application mapping are done in a relative short period. Yet we obtain C-programmed real-time H.264/AVC CIF decoding at 50 MHz. The die size, clock speed and the power consumption are also very competitive compared with other processors.

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC

“…However, only WVGA decoding can be achieved at 430 MHz. ADRES [15], which is one of the most successful reconfigurable architectures, supports Table 4 The execution time of different cases. 30 fps H.264 decoding at resolutions up to D1 when using a VLIW processor with a 7 × 7 CGRA accelerator.…”

“…However, because they cannot execute instructions concurrently, the code running on the VLIW processor and the remaining code that is accelerated on the reconfigurable array may not be pipelined efficiently. In previous study [15], a H.264/AVC CIF decoding at 56 MHz is implemented on ADRES.…”

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach

“…Owing to the remarkable configuration performance improvement, our CGRA can realize real-time H.264 high-profile decoding at the speed of 1080p@40 fps with the power consumption of 364 mW. ADRES [5] was designed to perform real-time (30 fps) H.264 baseline profile D1 decoding, which used a centralized context cache called configuration RAM to hold the current active configuration context for certain tasks. The architecture of XPP [7] was based on a scalable array attached with the configuration managers (CM), which was composed of hierarchical context caches including supervising CM and distributed CMs.…”

“…Many kinds of CGRAs have been proposed in recent years by employing context cache, whose structures can be classified into three categories including the centralized, the distributed and the hierarchical. In MorphoSys [3] and ADRES [4,5], a centralized context cache is shared by all reconfigurable resources. In sprit of the advantage of low hardware complexity for supervision, the configuration performance degrades heavily due to access conflict in the configuration cache.…”

Coarse-Grained Reconfigurable Array Architectures

“…Conceptually, these terms all denote the same: logic on which an instruction can be executed, typically one per cycle. For example, a typical ADRES [5,6,7,15,37,39,40,41] CGRA consists of 16 ISs, whereas the TI C64 features 8 slots, and the NXP TriMedia features only 5 slots. The higher number of ISs directly allows to reach higher IPCs, and hence higher performance, as indicated by Equation (1).…”