Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach

Abstract

This paper proposes a novel coarse-grained reconfigurable array (CGRA) with hierarchical context cache structure and efficient cache management approaches, including time-frequency weighted (TFW) context cache replacement strategy and context multi-casting (CMC) mechanism. By fully exploiting inherent configuration features, the configuration performance is improved by 18.2% with half context memory cost. Our CGRA was implemented under the process of TSMC 65 nm, which can work at the frequency of 200 MHz with the area of 23.2 mm 2 . Compared to the previous CGRAs, our work has the advantage of 3.8∼12× performance improvement and 2.3∼15.7× energy efficiency increase.

A SLM-based overlay architecture for fine-grained virtual FPGA

“…C. Wang et al proposed a novel coarse-grained reconfigurable array (CGRA) with hierarchical context cache structure and efficient cache management approaches, including time-frequency weighted (TFW) context cache replacement strategy and context multi-casting (CMC) mechanism. CGRA was implemented under the process of TSMC 65nm, frequency 200MHz, and area 23.2 mm 2 [8]. For fine-grained overlay implementation, Brant et al proposed ZUMA in [2].…”