Impact Of Trench Sidewall Interface Trap In Shallow Trench Isolation On Junction Leakage Current Characteristics For Sub-0.25 /spl mu/m CMOS Devices

Abstract

A methodology of direct characterization of interface traps in trench sidewall in STI structure is presented for the first time. It is demonstrated that n+/p-well diode in STI structure, which has large perimeter component of junction leakage, shows high D,t(-5X10" cm.' e V 1 near midgap) in trench sidewall. Successful reduction of junction leakage current is achieved by further hydrogen passivation of interface traps. Residual bulk traps are distributed within 25 nm from the surface. However, they would not contribute to junction leakage current because of smaller capture cross section.

Ionizing radiation effects on CMOS imagers manufactured in deep submicron process

“…It clearly demonstrates that these generation currents are only due to generation centers located on the perimeter of the photodiodes. This agrees with previous work 15, 16 which emphasized the important role of junction perimeter in LOCOS (local oxidation of silicon) and STI technologies. It also strongly suggests that ionizing radiation enhances this generation process.…”

3-D TCAD Study of the Implications of Channel Width and Interface States on FD-SOI Z2-FETs

“…The traps presence is especially hard to mitigate since the crystal orientation is not perfectly controlled in volume production. Furthermore, the STI process induces mechanical stress at the edges due to trench fabrication or thermal processes increasing the number of traps through lattice distortion and/or dislocation formation [14], [15].…”

Impact of gate induced drain leakage on overall leakage of submicrometer CMOS VLSI circuits

“…The recently published data [28], [29] show that shallow trench isolation (STI) structures have high interface trap density in trench sidewalls. As a result the junction leakage current is significantly increased when active regions of transistor are located close to trench sidewalls.…”