Impact of Synaptic Device Variations on Classification Accuracy in a Binarized Neural Network

Abstract

Brain-inspired neuromorphic systems (hardware neural networks) are expected to be an energy-efficient computing architecture for solving cognitive tasks, which critically depend on the development of reliable synaptic weight storage (i.e., synaptic device). Although various nanoelectronic devices have successfully reproduced the learning rules of biological synapses through their internal analog conductance states, the sustainability of such devices is still in doubt due to the variability common to all nanoelectronic devices. Alternatively, a neuromorphic system based on a relatively more reliable digital-type switching device has been recently demonstrated, i.e., a binarized neural network (BNN). The synaptic device is a more mature digital-type switching device, and the training/recognition algorithm developed for the BNN enables the task of facial image classification with a supervised training scheme. Here, we quantitatively investigate the effects of device parameter variations on the classification accuracy; the parameters include the number of weight states (Nstate), the weight update margin (ΔG), and the weight update variation (Gvar). This analysis demonstrates the feasibility of the BNN and introduces a practical neuromorphic system based on mature, conventional digital device technologies.

Fully CMOS-compatible passive TiO2-based memristor crossbars for in-memory computing

“…On the contrary, an off-chip (ex situ) training strategy is more sensitive to device variations since the training is performed using a software-based neural network where trained synaptic weights need to be transferred to the network [15]. In this case, the off-chip training accuracy can be largely affected if there are nonworking devices or a drift in device conductance programming [16]. Some of these device variations can be readily attributed to imperfections in the fabrication process [17] [18].…”

Effect of the Gate Dielectric Layer of Flexible InGaZnO Synaptic Thin-Film Transistors on Learning Behavior

“…This implies that the weight matrix is not saturated and cannot be optimized with the nonlinear weight modulation because of the abrupt weight transition by the occasional extraordinary training sample. These learning behaviors can be further eased by adopting the binarized neural network or off-chip learning method. , …”

“…These learning behaviors can be further eased by adopting the binarized neural network or off-chip learning method. 7,53 In addition, the effect of the weight window of the synaptic devices on the recognition rate is analyzed by introducing the V T variation to the weight map obtained at epoch = 50 for both devices as shown in Figure 6d with 20 trials. Since the synaptic current has a nonlinear relation with gate bias unlike two-terminal memristive devices, the current difference according to the V T variation is determined by the parabolic transfer curves in Figure 2b.…”

Exploiting defective RRAM array as synapses of HTM spatial pooler with boost-factor adjustment scheme for defect-tolerant neuromorphic systems

“…2 b. Here, it is preferable to obtain an RRAM with a large on/off ratio, taking into account the case, where each state can be overlapped by the stochastic nature of the ion migration 33 , 34 . Assuming that the number of achievable states is the same in the RRAM, the large on/off ratio ensures a reasonable margin between the states despite the inherent variability.…”