Impact of Process Variations on Pulsed Flip-Flops: Yield Improving Circuit-Level Techniques and Comparative Analysis

Abstract

Abstract. Process variations cause unpredictability in speed and power characteristics of nanometer CMOS circuits impacting the timing and energy yields. In this paper, transistor reordering and dual-Vth techniques are evaluated regarding their efficiency in mitigating the impact of process variations on a set of pulsed flip-flops. It is shown that the conjunct use of the above mentioned techniques can improve delay, energy and EDP yields more than 1.98X, 1.62X and 1.99X times, respectively. The yield optimized flip-flop circuits are also comparatively analyzed to identify the best topologies.

Flip-Flop Design in Nanometer CMOS

“…The variability of each parameter is reported for variations at three standard deviations around the mean value, as typically done in comparative evaluation of variations, [51,52,76,81,127,NKR07]. Extension to different number of standard deviations is straightforward and hence omitted.…”

“…Until now, various analyses and comparisons have been published that evaluate the impact of variations on Flip-Flops [44,51,52,72,75,76,81,97,123,126]. Unfortunately, these analyses are restricted to few topologies (at most [4][5] in the existing Flip-Flop classes.…”

“…Unfortunately, these analyses are restricted to few topologies (at most [4][5] in the existing Flip-Flop classes. In particular, the analysis in [123] is limited to static FFs, [76] is restricted to pulsed latches, [51] applies only to MTCMOS topologies, [75] is restricted to only one subthreshold topology, [77] focuses on race immunity and considers only transmission-gate based FFs, [44,52,72,81] analyze various classes of FFs but considers only 4 or 5 topologies in total. In addition, previous variation-aware analysis and design methodologies (see, e.g., [81,126]) do not include fundamental aspects such as the impact of layout parasitics in the circuit design loop, leakage, and parameters quantifying the interaction of Flip-Flops with the variations in the clock network design (e.g., skew induced by clock slope variations).…”

Analysis and comparison of variations in double edge triggered flip-flops

“…Hence, in real-world microprocessors the number of standard deviations to be considered ranges from 3 to 6, depending on the FF count. Nevertheless, in the following the results are presented at three standard deviations, as typically done in comparative evaluation of variations [20]- [25]. Extension to different number of standard deviations is straightforward and hence omitted.…”

Comparative analysis of yield optimized pulsed flip-flops

“…This paper is an extension of our previous work [10]. Two different circuit-level techniques are evaluated to mitigate the impact of process variations on pulsed FFs: the transistor reordering [11] and the usage of dual threshold voltage (DVT) transistors [12].…”