Impact of Parameter Variations and Random Dopant Fluctuations on Short-Channel Fully Depleted SOI MOSFETs With Extremely Thin BOX

Abstract

Characteristic variations of fully depleted siliconon-insulator (SOI) MOSFETs with extremely thin buried oxide are examined by device simulations. It is found, for the first time, that a SOI device with low channel impurity concentration and high substrate concentration has high immunity to both parameter variations and random dopant fluctuations (RDFs). Index Terms-Fully depleted (FD) silicon-on-insulator (SOI) MOSFET, random dopant fluctuation (RDF), thin buried oxide (BOX), variability.

Substrate impact on threshold voltage and subthreshold slope of sub-32 nm ultra thin SOI MOSFETs with thin buried oxide and undoped channel

“…Finally, the global increase of S with L G reduction is also in good qualitative agreement with [32] and with Skotnicki's model [9,[33][34][35] taking the effective front and back oxide thicknesses into account Eqs. (6) and (7). In that last model, an extra factor including the electrostatic integrity EIS, is introduced to account for the abrupt increase of S with the gate length reduction so that: V SUB is varying from À3 V to +3 V for UTB 2 and from À80 V to +80 V for UTB.…”

“…Thanks to the front gate-substrate charge coupling obtained with thin Si film on thick buried-oxide (BOX), almost ideal subthreshold swing and high transconductance levels are achieved. Undoped channel significantly reduces the random doping variability [6][7][8][9]. However, degradations and extra phenomena may still occur when reducing the gate length such as self-heating or fringing fields through the BOX and Si substrate [4,10,11].…”

Circuit design challenges at the 14nm technology node

“…It is expected that variability due to Random Dopant Fluctuations (RDF) will be improved [18,19,20]. Also, sub-threshold slopes are expected to improve, helping to allow lower device threshold voltages which in turn will facilitate lower voltage operation.…”

“…For ETSOI devices, the silicon film thickness will be a critical parameter, with even 1nm-scale thickness variations having significant impacts on the device threshold voltage for short channel devices [18]. ETSOI devices will escape the severe quantization effects associate with finFETs, but will probably see similar restrictions on multi-VT designs.…”

Performance and Area Scaling Benefits of FD-SOI Technology for 6-T SRAM Cells at the 22-nm Node

“…The primary causes for random variations in transistor threshold voltage (V TH ) are gate line-edge roughness (LER) and random dopant fluctuations (RDFs) [2]. A lightly doped (fully depleted, FD) siliconon-insulator (SOI) MOSFET structure with a very thin (∼10 nm thick) buried oxide (BOX) layer and a heavily doped substrate ("ground plane") has been shown to be effective for reducing the impact of parameter variations and RDF due to its excellent electrostatic integrity and the elimination of channel doping [3]. Recently, functional SRAM cells were demonstrated using such FD-SOI devices, for the 32 nm technology node and beyond [4].…”