Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

Villacorta, Hector; Gómez, R.; Bota, S.; Segura, J.; Champac, Victor

doi:10.1109/latw.2015.7102516

Cited by 4 publications

(4 citation statements)

References 9 publications

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“…6T-SRAM performance factors are shown in Table II. [30][31][32][33] In static operations, R P causes an observable effect under both read and write conditions. On the other hand, for dynamic evaluations, dummy gates cause a minimal increase in parasitic capacitance.…”

Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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A thorough investigation of the parasitic resistance and capacitance (RC) effects of a single-fin FinFET on logic CMOS devices and circuits is presented. As parasitic RC effects become increasingly prominent in nanoscaled FinFET technologies, they are critical to the overall device and circuit performance. In addition, the effects of dummy patterns as well as multifin structures are analyzed and modeled in detailed. By incorporating parasitic resistance and capacitance extracted by both measurement and simulation, the static and dynamic performance characteristics of standard six transistor static random-access memory (6T-SRAM) cells are comprehensively evaluated as an example of parasitic RC effects in this investigation.

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Section: Discussion On Parasitic Effects In 6t-srammentioning

confidence: 99%

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Huang¹,

Meng²,

King³

et al. 2017

Jpn. J. Appl. Phys.

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“…The use of a Weibull distribution to calculate the soft error rate from the critical charge is only an approximation, but it has nevertheless shown good results for the 65nm node, when compared to silicon measurements [16] and it has been also applied to FinFET technology [11], [17]. Following the SER estimation methodology used in [11], the charge collection efficiency can be computed from the linear energy transfer (LET) value, estimated to 50 fC/μm at ground level for neutrons impacting silicon.…”

Section: Simulation Of Radiation Effectsmentioning

confidence: 99%

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm

Royer

García‐Redondo

López‐Vallejo

2015

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH´15)

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New CMOS technologies such as SOI or FinFET are expected to enhance SRAM radiation-induced soft error rates thanks to a reduction on the charge collected as the devices get smaller. In this work we analyze how the radiation hardening capabilities of SRAMs are affected when process variations are considered by simulating cells using a predictive FinFET technology.The results show that even if the average critical charge to which SRAM cells are vulnerable is enhanced by process variations, its widened spread leads to an increase of the soft error rate by more than 40% as the technology node is scaled down to 7nm.

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“…In recent studies, the soft-error performance of a 6T SRAM cell has been analyzed with sub-nanometer devices. It was found that the FinFET-based SRAM cell showed better immunity due to soft error in comparison with its conventional counterpart, the CMOS SRAM cell [11][12][13]. Moreover, in the literature, a technique called radiation hardening by design (RHBD) is used to eliminate the effect of SEU during circuit level implementation [14][15][16].…”

Section: Introductionmentioning

confidence: 99%

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

et al. 2023

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In this paper, a soft-error-aware radiation-hardened 6T SRAM cell has been implemented using germanium-based dopingless tunnel FET (Ge DLTFET). In a circuit level simulation, the device-circuit co-design approach is used. Semiconductor devices are very prone to the radiation environment; hence, finding out the solution to the problem became a necessity for the designers. Single event upset (SEU), also known as soft error, is one of the most frequent issues to tackle in semiconductor devices. To mitigate the effect of soft error due to single-event upset, the radiation-hardening-by-design (RHBD) technique has been employed for Ge DLTFET-based SRAM cells. This technique uses RC feedback paths between the two cross-coupled inverters of an SRAM cell. The soft-error sensitivity is estimated for a conventional and RHBD-based SRAM cell design. It is found that the RHBD-based SRAM cell design is more efficient to mitigate the soft-error effect in comparison to the conventional design. The delay and stability parameters, obtained from the N-curve, of the Ge DLTFET-based SRAM cell performs better than the conventional Si TFET-based SRAM cell. There is an improvement of 305x & 850x in the static power noise margin and write trip power values of the Ge DLTFET SRAM cell with respect to the conventional Si TFET SRAM cell.

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Impact of increasing the fin height on soft error rate and static noise margin in a FinFET-based SRAM cell

Cited by 4 publications

References 9 publications

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Investigation of parasitic resistance and capacitance effects in nanoscaled FinFETs and their impact on static random-access memory cells

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm

Soft-Error-Aware Radiation-Hardened Ge-DLTFET-Based SRAM Cell Design

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