Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Villacorta, Hector; Segura, J.; Champac, Victor

doi:10.1007/s10836-016-5591-3

Cited by 9 publications

(3 citation statements)

References 13 publications

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“…The simulation results show that the device has a threshold voltage (V th ) of 0.328 V, a subthreshold swing (SS) of 68.713 mV/dec, a transconductance (g m ) of 1.16 ×10 −4 S, and a current switching ratio (I on /I of f ) of 2.52 ×10 6 . In contrast, the device has a cutoff frequency of 2.96 ×10 11 Hz, which can be derived from the CV characteristics simulation.…”

Section: A Device Structurementioning

confidence: 99%

Prediction of Single Event Effects in FinFET Devices Based on Deep Learning

Liu,

Wang,

Zhao

et al. 2023

IEEE J. Electron Devices Soc.

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The Single Event Effect (SEE) of FinFET devices has become one of the challenging issues affecting the reliability of modern electronic systems in space and terrestrial applications. However, the conventional FinFET device simulation steps are tedious and take a long time. This paper proposes a method based on a convolutional neural network (CNN) to predict the single event effect (SEE) of FinFET devices. By entering different particle incidence conditions, the SEE profiles, as well as the characteristic parameters, can be obtained quickly and accurately. The neural network model used in the experiments has a high prediction accuracy. The error of our trained network model in predicting the drain transient current pulse profile is only 0.012, The Mean Square Error(MSE) for predicting the peak drain transient current and total collected charge are only 0.00207 and 0.00084.The total time for training, validation and prediction of the neural network model in this study is 352 seconds, and the prediction time is much shorter, which is much lower than the simulation time of TCAD software. The minimum simulation time of the TCAD simulation software is 1901 seconds, and the simulation requires further modification of the resultant plots of the single event effect transient current curves.

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Section: A Device Structurementioning

confidence: 99%

Prediction of Single Event Effects in FinFET Devices Based on Deep Learning

Liu,

Wang,

Zhao

et al. 2023

IEEE J. Electron Devices Soc.

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“…A relationship is obtained by placing Y = Hfin / n(n≠0) in ( 25) between ψS1(z) and ψy(z). Now, replacing n=y/Hfin, thepotential distributionof the asymmetric DM TFET [25]…”

Section: + (14)mentioning

confidence: 99%

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Dharmireddy¹

2021

TURCOMAT

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This paper proposed on basis of a perimeter-weighted-sum method for the construction of a 3D-Analytical Modeling of double metalFin structure TFET with dual hetero gate oxide structure. The DM model device dividing into a symmetrical and asymmetrical dual-gate TFETs, and then resolving 3D architectures. The surface potential and the electrical field (E) achieved by resolving the Poisson 3D equation. The drain current (ID) is eventually calculated using Kane tunneling model to calculate the tunneling generation rate. Threshold voltage model also developed based on the charge inversion model. The performance analysis of dual hetero gate oxide Fin TFET device together with dual dielectric engineering techniques results in enhanced drain current and reduced SCE’s of low leakage current, threshold voltage roll-off and drain induced barrier lowering.

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“…This design approach improves the electrostatic control of the transistor's channel [21] and hence solves some of the before mentioned problems evolving CMOS technology for nodes beyond 22 nm. In more detail, leakage current, Short-Channel Effects (SCE) and Random Dopant Fluctuations (RDF) are mostly eliminated as doping levels are reduced to a minimum in FinFETs [34]. Consequently, the majority of microelectronic companies are gradually replacing CMOS transistors by FinFETs in their state-of-the-art processors.…”

Section: Introductionmentioning

confidence: 99%

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

et al. 2020

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CMOS technology scaling has reached its limit at the 22 nm technology node due to several factors including Process Variations (PV), increased leakage current, Random Dopant Fluctuation (RDF), and mainly the Short-Channel Effect (SCE). In order to continue the miniaturization process via technology down-scaling while preserving system reliability and performance, Fin Field-Effect Transistors (FinFETs) arise as an alternative to CMOS transistors. In parallel, Static Random-Access Memories (SRAMs) increasingly occupy great part of Systems-on-Chips' (SoCs) silicon area, making their reliability an important issue. SRAMs are designed to reach densities at the limit of the manufacturing process, making this component susceptible to manufacturing defects, including the resistive ones. Such defects may cause dynamic faults during the circuits' lifetime, an important cause of test escape. Thus, the identification of the proper faulty behavior taking different operating conditions into account is considered crucial to guarantee the development of more suitable test methodologies. In this context, a comparison between the behavior of a 22 nm CMOS-based and a 20 nm FinFET-based SRAM in the presence of resistive defects is carried out considering different power supply voltages. In more detail, the behavior of defective cells operating under different power supply voltages has been investigated performing SPICE simulations. Results show that the power supply voltage plays an important role in the faulty behavior of both CMOS-and FinFET-based SRAM cells in the presence of resistive defects but demonstrate to be more expressive when considering the FinFET-based memories. Studying different operating temperatures, the results show an expressively higher occurrence of dynamic faults in FinFET-based SRAMs when compared to CMOS technology.

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Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability

Cited by 9 publications

References 13 publications

Prediction of Single Event Effects in FinFET Devices Based on Deep Learning

Prediction of Single Event Effects in FinFET Devices Based on Deep Learning

3D Analytical Modeling Of Surface Potential And Threshold Voltage Model Of Dm Fintfet With Dual Hetero Gate Oxide Structure

Comparing the Impact of Power Supply Voltage on CMOS- and FinFET-Based SRAMs in the Presence of Resistive Defects

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