ICM2 IC: A new ATM switching element for 2.48 Gb/s communications

Calvo, F.; Plaza, P.; Mateos, P.

doi:10.1109/edtc.1994.326897

Cited by 4 publications

(2 citation statements)

References 3 publications

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“…The switching function is performed using self routing spatial techniques [4,5]. The scalable switching fabric is built by interconnecting ICM circuits [6].…”

Section: Architecturementioning

confidence: 99%

Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

Díaz

Plaza

Merayo

et al.

Proceedings. 1995 IEEE International Verilog HDL Conference

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This paper describes the design anld validation of a complex ASIC through the use of Verilog HDL. The CMC is an interface circuit for ATM cells, part of a 2.5 Gb/s switching fabric. Its main function is serial to pardlel and parallel to serial data conversion; another features like VPINCI translation, cell counting, insertion and extraction from an external microprocessor are also included. The validation and veriJication of the circuit implementation was carried out by simulating the different level of abstractions of the circuit descriptions thoroughly with Verilog-XL. Ar;r ECL cell Verilog library was written to be able to perform simulations of the complete circuit.The CMC is a 0.7 um BiCMOS IC, containing ECL and CMOS blocks. The complexity of the circuit is 320 Ktransistors on a die size of 224 nrm2. It has been encapsulated on a 319 pins CPGA package, dissipating 8.2 Watts at full speed.1 The ATM switch architecture and it:s high level validation. ArchitectureATM is becoming the most accepted network technology for Broadband ISDN. Its bandwidth-ondemand feature offers two advantages: flexibility and statistical gain. While a worldwide consensus exists on the first point, statistical gain seems to be difficult to obtain. performance calculations have shown statistical gain is obtained when the link bit rate is much larger than the source bit rate [l].The current ATM technology handles 155 Mb/s link bit rates, and only sources with few Mb/s bit rates would take advantage of statistical gain effect. The solution for higher bit rate sources is to develop ATM links operating at 2.5 Gb/s or more.The ClMC circuit is part of a switching fabric able to process four 2.5 Gb/s ATM input links [2,3]. The switching function is performed using self routing spatial techniques [4,5]. The scalable switching fabric is built by interconnecting ICM circuits [6]. The CMC converts ATM cells into an internal data parallel format: rnicrocells (slices of the ATM cell plus extra information for switching addressing, error detection [

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“…The switching function is performed using self routing spatial techniques [4,5]. The scalable switching fabric is built by interconnecting ICM circuits [6].…”

Section: Architecturementioning

confidence: 99%

Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

Díaz

Plaza

Merayo

et al.

Proceedings. 1995 IEEE International Verilog HDL Conference

Self Cite

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“…Its maximum operating rate is 2.5 Gb/s. The switch core is implemented with only one IC, the ICM2 [4]. A switching fabric is constructed by interconnecting several ICM2 chips together, therefore it is an scaleable architecture.…”

Section: -Introduction To the Atm Switchmentioning

confidence: 99%

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC

Plaza¹,

Diaz²,

Calvo³

et al.

Proceedings the European Design and Test Conference. ED&TC 1995

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Test cost/coverage tradeoffs in complex telecommunication circuits

Aguado¹

The Third Annual Atlantic Test Workshop

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Cost and q a t y are m c i a l pt my pmjsct development. These p,arpmetwr an strongly lntcnolated and muit be taken m m account from tht rutting phases of the development 14owcver, in general, clpssicdi test mlr pn not nuible with thee osptcts, 1t is, they do not allow the designer to nduce t a t COS^ at the eapcnsc of a muumlrm loss in fault covarage In thir paper, the e r p e n c e of Teleffinica I+D concerning the rmuiagement of test c m t bnd quhIJ factors Will be p e n t c d Wphasis will k apphed U, show the main problems U9.U h v e rppeid to sonarht6 the test of two high complcxlry telecommurucatlon ASIC3 1.-Introduction.The main objective of resting mlr is to obuun m a r i " fault coverages in tauionable CPU rimes using a pradsfined Design for Testability smtcp. This march u n d tt'st objectives in ASIC dediip. However, it is also nscaosq lo dtoign some circuits for which asstino cost rspl&cts are decisive, bVill8 priority 0ve.r the covmgc ones At TcleflSnica 1+D, test cost problem M: usually given in ]prototype ASIC8 for demonstrators. These are hieh complexity ASICs. with a high deslgn IriBk (as they are tiesigned bordering on the tehnology m u ) , md CharrctrriLed also by the s m d numkr of fabricated pieces. Cast prObkm6 cdn be centc.,rd on extra cue8 for tasting, on the rpssd perfmmce penalty or on the teat applicrttion w t . In these CLSOI, i t k; usually d e d to rccept tome risk by rodwing test cats au the expense of a Iowa fault covstulgc.

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ICM2 IC: A new ATM switching element for 2.48 Gb/s communications

Cited by 4 publications

References 3 publications

Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

Design and validation with HDL Verilog of a complex input/output processor for an ATM switch: the CMC

Input and output processor for an ATM high speed switch (2.5 Gb/s): the CMC

Test cost/coverage tradeoffs in complex telecommunication circuits

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