This paper presents the structure of the Distributed Computing ATPG System DPLATON, with special emphasis on the distribution strategy basis and the communication structures implemented. The proposed system is based on a dynamic fault listpartition criterion. The standard Remote Procedure Call (RPC) and Emem1 Data Representation (XDR) mechanisms have been adapted to construct an Ocient dynamic distributed implementation. Reduced test sets and important CPU time speed-up factors are reported.
Cost and q a t y are m c i a l pt my pmjsct development. These p,arpmetwr an strongly lntcnolated and muit be taken m m account from tht rutting phases of the development 14owcver, in general, clpssicdi test mlr pn not nuible with thee osptcts, 1t is, they do not allow the designer to nduce t a t COS^ at the eapcnsc of a muumlrm loss in fault covarage In thir paper, the e r p e n c e of Teleffinica I+D concerning the rmuiagement of test c m t bnd quhIJ factors Will be p e n t c d Wphasis will k apphed U, show the main problems U9.U h v e rppeid to sonarht6 the test of two high complcxlry telecommurucatlon ASIC3
1.-Introduction.The main objective of resting mlr is to obuun m a r i " fault coverages in tauionable CPU rimes using a pradsfined Design for Testability smtcp. This march u n d tt'st objectives in ASIC dediip. However, it is also nscaosq lo dtoign some circuits for which asstino cost rspl&cts are decisive, bVill8 priority 0ve.r the covmgc ones At TcleflSnica 1+D, test cost problem M: usually given in ]prototype ASIC8 for demonstrators. These are hieh complexity ASICs. with a high deslgn IriBk (as they are tiesigned bordering on the tehnology m u ) , md CharrctrriLed also by the s m d numkr of fabricated pieces. Cast prObkm6 cdn be centc.,rd on extra cue8 for tasting, on the rpssd perfmmce penalty or on the teat applicrttion w t . In these CLSOI, i t k; usually d e d to rccept tome risk by rodwing test cats au the expense of a Iowa fault covstulgc.
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