Test cost/coverage tradeoffs in complex telecommunication circuits

Abstract

Cost and q a t y are m c i a l pt my pmjsct development. These p,arpmetwr an strongly lntcnolated and muit be taken m m account from tht rutting phases of the development 14owcver, in general, clpssicdi test mlr pn not nuible with thee osptcts, 1t is, they do not allow the designer to nduce t a t COS^ at the eapcnsc of a muumlrm loss in fault covarage In thir paper, the e r p e n c e of Teleffinica I+D concerning the rmuiagement of test c m t bnd quhIJ factors Will be p e n t c d Wphasis will k apphed U, show the main problems U9.U h v e rppeid to sonarht6 the test of two high complcxlry telecommurucatlon ASIC3 1.-Introduction.The main objective of resting mlr is to obuun m a r i " fault coverages in tauionable CPU rimes using a pradsfined Design for Testability smtcp. This march u n d tt'st objectives in ASIC dediip. However, it is also nscaosq lo dtoign some circuits for which asstino cost rspl&cts are decisive, bVill8 priority 0ve.r the covmgc ones At TcleflSnica 1+D, test cost problem M: usually given in ]prototype ASIC8 for demonstrators. These are hieh complexity ASICs. with a high deslgn IriBk (as they are tiesigned bordering on the tehnology m u ) , md CharrctrriLed also by the s m d numkr of fabricated pieces. Cast prObkm6 cdn be centc.,rd on extra cue8 for tasting, on the rpssd perfmmce penalty or on the teat applicrttion w t . In these CLSOI, i t k; usually d e d to rccept tome risk by rodwing test cats au the expense of a Iowa fault covstulgc.