ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

Lai, Victor; Diessel, Oliver

doi:10.1109/fpt.2009.5377616

Cited by 21 publications

(9 citation statements)

References 3 publications

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“…We could potentially get similar values as the theoretical ones, by using a FSM as the configuration controller and downloading the configuration bitstream using "bit-parallel" mode. Furthermore, we are investigating the existing ICAP architectures and design techniques used in [16,18,25,27] and planning to explore ways to design and incorporate similar techniques, to enhance the reconfiguration process.…”

Section: Discussionmentioning

confidence: 99%

“…There is several existing research work on enhancing the ICAP architecture in order to accelerate the reconfiguration flow [16,18,25,27]. We are currently investigating these architectures and design techniques, and planning to explore ways to design and incorporate similar techniques, which could potentially reduce the reconfiguration time overhead of our current reconfigurable hardware designs.…”

Section: Time Overhead For Reconfigurationmentioning

confidence: 99%

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Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Shahrouzi

Perera

2017

J Embedded Systems

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With the advancement of mobile and embedded devices, many applications such as data mining have found their way into these devices. These devices consist of various design constraints including stringent area and power limitations, high speed-performance, reduced cost, and time-to-market requirements. Also, applications running on mobile devices are becoming more complex requiring significant processing power. Our previous analysis illustrated that FPGA-based dynamic reconfigurable systems are currently the best avenue to overcome these challenges. In this research work, we introduce efficient reconfigurable hardware architecture for principal component analysis (PCA), a widely used dimensionality reduction technique in data mining. For mobile applications such as signature verification and handwritten analysis, PCA is applied initially to reduce the dimensionality of the data, followed by similarity measure. Experiments are performed, using a handwritten analysis application together with a benchmark dataset, to evaluate and illustrate the feasibility, efficiency, and flexibility of reconfigurable hardware for data mining applications. Our hardware designs are generic, parameterized, and scalable. Furthermore, our partial and dynamic reconfigurable hardware design achieved 79 times speedup compared to its software counterpart, and 71% space saving compared to its static reconfigurable hardware design.

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Section: Discussionmentioning

confidence: 99%

Section: Time Overhead For Reconfigurationmentioning

confidence: 99%

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Shahrouzi

Perera

2017

J Embedded Systems

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“…ere are other existing PRCs proposed in the literature that are designed for standalone usage in hardware designs without any supporting processor [16][17][18][19]. Unfortunately their design files are not publicly available, with the exception of [20].…”

Section: Related Workmentioning

confidence: 99%

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Kirchhoff

Kerling

Streitferdt

et al. 2019

International Journal of Reconfigurable Computing

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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“…The reconfiguration controller, XCTRL, manages the reconfiguration process of the system. The memory (ZBT-SRAM) stores both bitstream and application data, and when one region is being reconfigured, the ICAP-I module [18] schedules the bitstream traffic and the application data of the other region. Thus the memory and the the ICAP-I forms the shared datapath between the application layer and the reconfiguration layer (shown as both lightly and darkly shaded boxes).…”

Section: Case Studiesmentioning

confidence: 99%

ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration

Gong

Diessel

2011

2011 International Conference on Field-Programmable Technology

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Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array (FPGA) to be reconfigured while the rest continues to operate. However, such flexibility introduces challenges for verifying DPR design functionality because there is no straightforward way to simulate DPR at Register Transfer Level (RTL). This paper proposes the ReSim library to enable the RTL simulation of DPR. The library uses a simulation-only layer to hide the physically dependent details of DPR designs while providing sufficient accuracy for functional verification. The library is extensible and reusable. We assess the feasibility and demonstrate the value of our tool via two case studies of DPR designs.

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ICAP-I: A reusable interface for the internal reconfiguration of Xilinx FPGAs

Cited by 21 publications

References 3 publications

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

Dynamic partial reconfigurable hardware architecture for principal component analysis on mobile and embedded devices

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

ReSim: A reusable library for RTL simulation of dynamic partial reconfiguration

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