A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Abstract

Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

Simple Adaptive Control‐Based Reconfiguration Design of Cabin Pressure Control System

“…First of all, the proposed method greatly reduces the complexity and difficulty of implementation compared with other adaptive controls. Secondly, there are many FPGAbased reconfiguration projects for [55,56]. us, the proposed method can be designed based on them.…”

VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC

“…MiCAP-Pro is the advanced version of the basic MiCAP in which the reconfiguration throughput is increased up to 272 MB/s by the addition of a DMA engine and an HP port. Another partial reconfiguration controller (PRC) mentioned in [13] has microblaze processor-based architecture instead of ZynQ. At one time, two words of bitstream can be sent due to the 64-bit data width of the bus, which makes it very fast.…”

“…The PCAP does not provide a software API for frame-level fine-grain reconfiguration [9]. Custom ICAP controllers have been shown to achieve a throughput that is quite close to the theoretical limit; i.e., 380+ MB/s in some cases [10][11][12][13][14][15][16][17][18][19]. However, except for the author in [16], no researchers support the fine-grain reconfiguration of primitive FPGA elements; e.g., LUTs.…”

Dynamic Partial Reconfiguration Profitability for Real-Time Systems

“…Since the DPR produces a change in the HW architecture, it can be used to improve task performances in terms of timing and/or power. These potentialities make the DPR process highly desirable in a wide range of systems, such as hard (e.g., [1], [2], [3], [4]) and soft real-time systems (e.g., [5], [6]). With respect to a full design-time approach, possible advantages can be, e.g., to allow schedulability of a given task set also in the case where the available FPGA resources are not enough to host all the HW tasks at the same time [2], or to keep schedulability also in the case of a run-time changing task set by moving some of the tasks in HW.…”

“…However, as highlighted in [1] in 2017, all the components of the RP need to be considered to guarantee a worst-case bound of the DPR time (i.e., worst-case DPR time, wcdprt). In fact, after an in-depth analysis of the literature, we discovered that only the works in [1], [3] and [4] propose an approach to calculate the wcdprt considering this dependency. However, such approaches are based on ad-hoc architectural elements, making them target-dependent.…”