Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Valente, G.; Mascio, Tania Di; Pomante, Luigi; D'Andrea, Gabriella

doi:10.1109/les.2020.3004302

Cited by 20 publications

(3 citation statements)

References 8 publications

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“…They applied these results in the development of a runtime reconfiguration support under WCET guarantees. Valente et al [10] proposed a detailed characterization of the components involved in the reconfiguration in order to provide a worst-case bound on the cost. This result allowed them to define the profitability of the DPR reconfiguration in real-time systems.…”

Section: Related Workmentioning

confidence: 99%

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration

Pagani

Biondi

Marinoni

et al. 2022

Future Generation Computer Systems

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Computing platforms for next-generation cyber-physical systems are evolving towards heterogeneous architectures comprising different processing elements and hardware accelerators. In particular, SoC-FPGA platforms, including multiple general-purpose processing cores tightly coupled with an FPGA fabric, represent an attractive solution due to their flexibility, efficiency, and timing predictability. On these platforms, dedicated hardware accelerators implemented on the FPGA fabric can offload computationally intensive activities from general-purpose processing cores. Furthermore, dynamic partial reconfiguration allows virtualizing the FPGA resources by sharing them among multiple hardware accelerators over time.Although very promising, FPGA-based hardware acceleration also introduces new challenges, such as managing and scheduling multiple concurrent acceleration and reconfiguration requests. The FRED framework has been proposed to address these challenges while preserving the predictability required by real-time systems. FRED is based on a device model that matches the capabilities of contemporary SoC-FPGA platforms and comes with an ad-hoc scheduling infrastructure designed to guarantee bounded response times for DPR-enabled accelerated tasks. This paper presents Fred-Linux, the reference implementation of the FRED framework for GNU/Linux. Fred-Linux allows developing rich applications while leveraging predictable FPGA-based hardware acceleration for performing heavy computations. Fred-Linux has been developed using the Zynq-7000 and Zynq-UltraScale+ by Xilinx as reference platforms, and it can be easily ported and extended on other platforms thanks to its modular design.

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Section: Related Workmentioning

confidence: 99%

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration

Pagani

Biondi

Marinoni

et al. 2022

Future Generation Computer Systems

View full text Add to dashboard Cite

show abstract

“…The run-time spatial-temporal exploitation of FPGA compute resources requires certain applications to fulfill some strict latency requirements in order not to suffer service downtimes. Different works tried to improve the PR latency and reconfiguration control overheads [9][10][11]. Another major setback for more widespread use of the PR methods is concerns related to data privacy and security when FPGA devices are used as shared computing resources in multi-tenant edge or cloud applications.…”

Section: Introductionmentioning

confidence: 99%

Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access Technologies

Bartzoudis,

Rubio Fernández,

López-Bueno

et al. 2024

Electronics

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This paper presents ReproRun, a flexible and extensible run-time framework for the reconfiguration of functions in field programmable gate array (FPGA) devices used in popular software-defined radio (SDR) platforms. The FPGA devices embed a hardwired or soft processing system (PS) which communicates with the programmable logic (PL) using a standard embedded bus interface. In order to apply a seamless run-time partial reconfiguration, we made use of all the related building blocks, design guidelines, and tools offered by AMD-Xilinx. In ReproRun, each partial bitstream targeting a reconfigurable region (RR) of the PL area comes with its respective firmware (i.e., software functions) that runs on the PS side. Our work guarantees run-time updates of the firmware without interrupting the functionality of other software processes running in the PS or PL, by employing a specialized controller, denoted as Run-timE firmWare reconfIguration contRollEr (REWIRE). The latter leverages the open asymmetric multiprocessing framework (OpenAMP). The partial bitstreams and respective firmware are fetched from a remote location using the trivial file transfer protocol (TFTP). ReproRun can be applied in different FPGA accelerators residing in disaggregated open radio access network (RAN) equipment, adaptive radio access technologies, and Edge servers hosting virtualized functions.

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“…In spite of the advantages of DPR systems compared to static logic systems, their complexity is a significant drawback in their implementation [20]. The recurrent issue designers must deal with when designing DPR systems is the difficulty to assert its behavioral characteristics in the application domain, such as the reconfiguration time [21], performance [22], power efficiency [23], and its impact on the device as a whole. This work makes use of a high-level modeling tool for DPR System of Chips (SoCs), named RTRLib [24], allowing non-expert users to develop run-time reconfigurable applications.…”

mentioning

confidence: 99%

Dynamic Reconfiguration for Multi-Magnet Tracking in Myokinetic Prosthetic Interfaces

Pertuz,

Mendes,

Gherardini

et al. 2024

Preprint

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Recently myokinetic interfaces have been proposed to exploit magnet tracking for controlling bionic prostheses. This interface derives information about muscle contractions from permanent magnets implanted into the amputee’s forearm muscles. Machine learning models have been mapped on Field Programmable Gate Arrays (FPGAs) to track a single magnet, achieving good precision and computational efficiency, but consuming a large area and hardware resources. To track several magnets, here we propose a novel solution based on dynamic partial reconfiguration, switching three prediction models: a linear regressor, a radial basis function neural network, and a multi-layer perceptron neural network. A system with five magnets and 128 magnetic sensor inputs was used and experimental data were collected to train a system with five hardware predictors. To reduce the complexity of the models, we applied principal component analysis, ranking by correlation the number of inputs of each model. This run-time reconfigurable solution allows the circuits to be reconfigured in order to select the most reliable predictor model for each magnet while the rest of the circuit continues to operate extracting the most significant information from the captured signals. Thus, the proposed solution remarkably reduces the hardware occupation and improves the computational efficiency compared to previous solutions.

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Dynamic Partial Reconfiguration Profitability for Real-Time Systems

Cited by 20 publications

References 8 publications

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration

A Linux-based support for developing real-time applications on heterogeneous platforms with dynamic FPGA reconfiguration

Agile FPGA Computing at the 5G Edge: Joint Management of Accelerated and Software Functions for Open Radio Access Technologies

Dynamic Reconfiguration for Multi-Magnet Tracking in Myokinetic Prosthetic Interfaces

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