Field{Programmable Gate Arrays (FPGAs) that allow partial recon guration at run{time can be shared among multiple independent tasks. When the sequence of tasks to be performed is unpredictable the FPGA controller needs to make allocation decisions on{line. Since on{line allocation su ers from fragmentation, tasks can end up waiting despite there being su cient, albeit non{contiguous resources available to service them. The time to complete tasks is consequently longer and the utilization of the FPGA is lower than it could be. We propose rearranging a subset of the tasks executing on the FPGA when doing so allows the next pending task to be processed sooner. We describe and evaluate methods for overcoming the NP{hard problems of identifying feasible rearrangements and scheduling the rearrangements when moving tasks are reloaded from o {chip.
Dynamic Partial Reconfiguration (DPR) enables software-like flexibility in hardware designs by allowing some of the logic on a Field Programmable Gate Array (FPGA) to be reconfigured while the rest continues to operate. However, such flexibility introduces challenges for verifying DPR design functionality because there is no straightforward way to simulate DPR at Register Transfer Level (RTL). This paper proposes the ReSim library to enable the RTL simulation of DPR. The library uses a simulation-only layer to hide the physically dependent details of DPR designs while providing sufficient accuracy for functional verification. The library is extensible and reusable. We assess the feasibility and demonstrate the value of our tool via two case studies of DPR designs.
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