Chip-Based Reconfigurable Task Management

Brebner, Gordon; Diessel, Oliver

doi:10.1007/3-540-44687-7_19

Cited by 43 publications

(23 citation statements)

References 13 publications

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“…Hopefully, the new free areas can accommodate the new incoming task. Compaction requires preemption, where running tasks are stopped and continued at a different location [3]. If all the running tasks are involved in the compaction process, then the compaction is total otherwise it is partial.…”

Section: Introductionmentioning

confidence: 99%

Improving utilization of reconfigurable resources using two-dimensional compaction

2007

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Partial reconfiguration allows parts of the reconfigurable chip area to be configured without affecting the rest of the chip. This allows placement of tasks at run time on the reconfigurable chip. Area management is a very important issue which highly affect the utilization of the chip and hence the performance.This paper focuses on a major aspect of moving running tasks to free space for new incoming tasks (compaction). We study the effect of compacting running tasks to free more contiguous space on the system performance. First, we introduce a straightforward compaction strategy called Blind compaction. We use its performance as a reference to measure the performance of other compaction algorithms. Then we propose a two-dimensional compaction algorithm called one-corner compaction. This algorithm runs with respect to one chip corner. We further extend this algorithm to the four corners of the chip and introduce the four-corners compaction algorithm. Finally, we compare the performance of these algorithms with some existing compaction strategies: ). The simulation results show improvement in average task allocation time when using the four-corners compaction algorithm by 15% and in chip utilization by 16% over the Blind compaction. These results outperform the existing strategies.

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Section: Introductionmentioning

confidence: 99%

Improving utilization of reconfigurable resources using two-dimensional compaction

2007

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“…The algorithmic challenge in developing a runtime system is to design effective and efficient algorithms for the scheduling and placement of hardware tasks. Such problems have been studied in, e.g., [1,15,8,13,10,3,9] and also under real time constaints in, e.g., [7,14]. Most authors assume a 2-dimensional area model where tasks are modeled as relocatable rectangles which can be placed anywhere on the FPGA device by partial reconfiguration.…”

Section: Introduction and Related Workmentioning

confidence: 99%

Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware

Danne

Platzner

2006

Proceedings 20th IEEE International Parallel &Amp; Distributed Processing Symposium

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“…This means operating on a single frame at a time is much slow er than operating on sev eral contiguous frames in one go, and is one reason w 2 w 1 . U sing the S onic-on-a-C hip platform (system C P U /bus clock speed 1 0 0 M H z , 1 H ow ev er, in both situations a large percentage of the configuration time is d ue to inefficiencies in the d riv er softw are, particularly w here d ata transfer is inv olv ed . Ignoring these inefficiencies one can d eriv e a low er bound to the inherent ov erhead .…”

Section: C O N Fi Gu R a Tio N O V E R H E A Dmentioning

confidence: 99%

Modular partial reconfiguration in virtex FPGAs

Sedcole

Blodget

Anderson

et al.

International Conference on Field Programmable Logic and Applications, 2005.

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Electron ic En g in eerin g , Im perial C olleg e L on d on , U K B r a n don B lodg et, J a m es A n der s on Pa tr ick L y s a g h t X ilin x , In c., 2 1 0 0 L og ic Driv e, S an J os e, C A 9 5 1 2 4 , U S A T ob ia s B eck er U n iv ers ität K arls ru h e (T H ), K ais ers traß e 1 2 -7 6 1 3 1 K arls ru h e, G erm an y ABSTRACT Modular systems implemented on Field-Programmable G ate A rrays c an benefi t from being able to load and unload modules at run-time, a c onc ept th at is of muc h interest in th e researc h c ommunity. W h ile dynamic partial rec onfi guration is possible in V irtex series and S partan series FPG A s, th e c onfi guration arc h itec ture of th ese dev ic es is not amenable to modular rec onfi guration, a limitation w h ic h h as relegated researc h to th eoretic al or c ompromised resourc e alloc ation models. In th is paper tw o meth ods for implementing modular dynamic rec onfi guration in V irtex FPG A s are c ompared and c ontrasted. T h e fi rst meth od offers simplic ity and fast rec onfi guration times, but limits th e geometry and c onnectiv ity of th e system. T h e sec ond meth od, rec ently dev eloped by th e auth ors, enables modules to be alloc ated arbitrary areas of th e FPG A , bridging th e gap betw een th eory and reality and unloc k ing th e latent potential of partial rec onfi guration. T h e later meth od h as been demonstrated in th ree applic ations. . I N TRO D U CTI O NT h e transistor density of Field Programmable G ate A rrays h as reac h ed a lev el w h ere an entire system may be implemented w ith in a single dev ic e. A c omplex system is generally c omposed from many func tionally disc rete modules, w h ic h are c onnec ted to form a c oh erent w h ole. In some c ases w h ere th e req uirements on th e system are time-v ariant, not all modules need to operate c onc urrently. A n unused module resident in th e FPG A w ill w aste pow er, area and c ost, and th erefore it w ould be adv antageous if modules are able to be loaded only w h en an applic ation is inv ok ed and remov ed again onc e th e applic ation h as terminated.T h ere h as been a large amount of researc h in th e area of dynamic modular systems in FPG A s [1 , 2 , 3 , 4 , 5 ]. T h ese are predic ated on th e property of dynamic partial rec onfi guration, h ow ev er module-based rec onfi guration h as not been intrinsic ally supported in FPG A s sinc e th e demise of th e * The authors wish to thank Jean Belzile, Normand Leclerc, Pierre-A ndré M eunier and D av id R ob erg e from IS R Technolog ies for their inv aluab le contrib utions, and also Peter C heung for his critiq ue of this p ap er.X ilinx 6 2 0 0 series. W h ile th e V irtex and S partan series of FPG A s are partially rec onfi gurable, th e essentially linear organisation of th e c onfi guration memory is not amenable to th e implementation of module-based systems w ith tw odimensional fl oorplans. A s a result researc h h as tended to be eith er th eoretic al, or sev erely c irc umsc ribed, typic ally by reduc ing th e resour...

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Chip-Based Reconfigurable Task Management

Cited by 43 publications

References 13 publications

Improving utilization of reconfigurable resources using two-dimensional compaction

Improving utilization of reconfigurable resources using two-dimensional compaction

Partitioned scheduling of periodic real-time tasks onto reconfigurable hardware

Modular partial reconfiguration in virtex FPGAs

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