Dynamic scheduling of tasks on partially reconfigurable FPGAs

Diessel, Oliver; ElGindy, Hossam A.; Middendorf, Martin; Schmeck, Hartmut; Schmidt, Bernd

doi:10.1049/ip-cdt:20000485

Cited by 97 publications

(71 citation statements)

References 10 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…FPGAs offer more flexibility than GPUs, and the flexibility can be used to obtain a better power-performance ratio [12]. Furthermore, FPGAs can support space-sharing, in addition to time-sharing, via partial reconfiguration using the methods in [13].…”

Section: Securing High-performance Computationmentioning

confidence: 99%

Security challenges and opportunities in adaptive and reconfigurable hardware

Costan

Devadas

2011

2011 IEEE International Symposium on Hardware-Oriented Security and Trust

View full text Add to dashboard Cite

Abstract-We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two paired chips. We show that making a Field-Programmable Gate Array (FPGA) a part of the TCB benefits security and performance, and we explore a new method for defending the computation inside the TCB against sidechannel attacks.

show abstract

Section: Securing High-performance Computationmentioning

confidence: 99%

Security challenges and opportunities in adaptive and reconfigurable hardware

Costan

Devadas

2011

2011 IEEE International Symposium on Hardware-Oriented Security and Trust

View full text Add to dashboard Cite

show abstract

“…One troubling aspect of other designs in the field [6,13,16,21] is the amount of time required to change the patterns in the unit, usually requiring some place-and-route effort and partial reconfiguration. While much work has been published on effective strategies for this [2,10], the schemes are never as effective as a system with architectural support for on-the-fly reconfiguration.…”

Section: Reconfiguration Of Arrays Of Unitsmentioning

confidence: 99%

A computationally efficient engine for flexible intrusion detection

Baker

Prasanna

2005

IEEE Trans. VLSI Syst.

View full text Add to dashboard Cite

Pattern matching for network security and intrusion detection demands exceptionally high performance. This paper describes a novel systolic array-based string matching architecture using a buffered, two-comparator variation of the Knuth-Morris-Pratt (KMP) algorithm. The architecture compares favorably with the state-of-the-art hardwired designs while providing on-the-fly reconfiguration, efficient hardware utilization, and high clock rates. KMP is a well-known, computationally-efficient string matching technique that uses a single comparator and a precomputed transition table. Through the use of the transition table, the number of redundant comparisons performed is reduced. Through various algorithmic changes, we enable KMP to be used in hardware, providing the computational efficiency of the serial algorithm and the high throughput of a parallel hardware architecture. The efficiency of the system allows for a faster and denser implementation than any other RAM-based exact match system. We add a second comparator and an input buffer, then prove that the modified algorithm can function efficiently implemented as an element of a systolic array. The system can accept at least one character in each cycle, while guaranteeing that the stream will never stall. In this paper, we prove the bound on the buffer size and running time of the systolic array, discuss the architectural considerations involved in the FPGA implementation, and provide performance comparisons against other approaches.

show abstract

“…Hardware multitasking on FPGAs and other reconfigurable hardware devices has been studied in, e.g., [6,5,8,9,10]. Most authors assume a 2-dimensional area model that assumes partial reconfigurability and treats tasks as relocatable rectangles which can be placed anywhere on the FPGA device.…”

Section: Related Workmentioning

confidence: 99%