I3T80: a 0.35 μm based system-on-chip technology for 42 V battery automotive applications

Moens, P.; Bolognesi, D.; Delobel, L.; Villanueva, Daniel; Hakim, H.; Trinh, Stephanie; Reynders, K.; Pestel, F. De; Lowe, A.; Backer, E. De; Herzeele, G. Van; Tack, M.

doi:10.1109/ispsd.2002.1016212

Cited by 26 publications

(7 citation statements)

References 5 publications

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“…2. The technology of choice for the presented work is the OnSemi I3T80 technology which incorporates a 0.35 µm CMOS process with floating high-voltage quasi-vertical nDMOS and lateral pDMOS transistors [9]. The implemented transistors have a maximum rated bulk drain voltage V bd of 70 V while the supply voltage needed to fully drive the piezoactuator is 72 V. However, the transistors have an avalanche breakdown voltage at or above 78.5 V which is the absolute upper voltage limit when the devices are in the off state.…”

Section: Driver Overview and Chip Technologymentioning

confidence: 99%

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

Pierco

Torfs

Verbrugghe

et al. 2015

IEEE Trans. Circuits Syst. I

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Abstract-A high-voltage, 16 channel driver with a maximum voltage of 72 volt and 14 bit resolution in a high-voltage CMOS (HV-CMOS) process is presented. This design incorporates a 14 bit monotonic by design DAC together with a high-voltage complementary class AB output stage for each channel. All 16 channels are used for driving a piezoelectric actuator within the control loop of a micropositioning system. Since the output voltages are static most of the time, a class AB amplifier is used, implementing voltage feedback to achieve 14 bit accuracy. The output driver consists of a push-pull stage with a builtin output current limitation and high-impedance mode. Also a protection circuit is added which limits the internal current when the output voltage saturates against the high-voltage rail. The 14 bit resolution of each channel is generated with a segmented resistor string DAC which assures monotonic by design behavior by using leapfrogging of the buffers used between segments. A diagonal shuffle layout is used for the resistor strings leading to cancellation of first order process gradients. The dense integration of 16 channels with high peak currents results in crosstalk, countered in this design by using staggered switching and re-sampling of the output voltages.

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Section: Driver Overview and Chip Technologymentioning

confidence: 99%

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

Pierco

Torfs

Verbrugghe

et al. 2015

IEEE Trans. Circuits Syst. I

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“…The presented PDEMOS is developed for the socalled I3T80 system-on-chip technology from Alcatel Microelectronics [4]. It is based on a 0.35 m standard 3.3 V CMOS platform, consisting of twin retrograde wells in a low doped N-epi on a P-substrate, a thin gate oxide and dual flavoured gates.…”

Section: Process and Device Descriptionmentioning

confidence: 99%

Cost Effective Implementation of a 90 V RESURF P-type Drain Extended MOS in a 0.35 um Based Smart Power Technology

Bakeroot

Vermandel

Moens

et al. 2002

32nd European Solid-State Device Research Conference

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This paper describes a 90 V, 300 m mm 2 RESURF P-type drain extended MOS (PDEMOS) transistor in a 0.35 m based smart power technology.The excellent performance of the device is realised with a dedicated Pdrift layer, designed to achieve maximum benefit from the RESURF effect. The proposed approach is very cost effective since there is only one extra mask for the Pdrift layer, no high-tilt implant (no extra mask for a Nbody) and no extra thermal budget.

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“…I3T50 has a 50V VDMOS transistor with self-aligned channel, as reported in [3]. A more cost effective I3T80 technology node is reported in [4] for an 80V integrated VDMOS transistor, using the Pwell of the standard CMOS as Pbody for the DMOS. The drawback of this option is the strong influence of the parasitic JFET transistor because of the gradually implanted Pwell, resulting in a deep bottleneck between each two adjacent Pbody stripes.…”

Section: Introductionmentioning

confidence: 99%

“…The present work is a continuation of that described in [4], with the objective of reducing the efficiency of the parasitic junction field effect transistor by mean of introducing an anti-JFE implant in the fabrication process. This article summarizes the TCAD and experimental results of this technique when applied for the improvement of an 80V DMOS transistor in I3T80.…”

Section: Introductionmentioning

confidence: 99%

Integrated VDMOS transistor with reduced JFET effect

Hakim

Bolognesi

Pestel

2006

2006 European Solid-State Device Research Conference

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In order to improve the trade-off between the breakdown voltage and the ON-state resistance of integrated VDMOS transistors, an anti Junction Field Effect implant has been introduced for an 80V Smart Power platform based on a 0.35µm CMOS node. Optimized dose and energy allow a reduction of the resistance without significant impact on the breakdown voltage and the other integrated components of the technology.

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I3T80: a 0.35 μm based system-on-chip technology for 42 V battery automotive applications

Cited by 26 publications

References 5 publications

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

A 16 Channel High-Voltage Driver with 14 Bit Resolution for Driving Piezoelectric Actuators

Cost Effective Implementation of a 90 V RESURF P-type Drain Extended MOS in a 0.35 um Based Smart Power Technology

Integrated VDMOS transistor with reduced JFET effect

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