Integrated VDMOS transistor with reduced JFET effect

Abstract

In order to improve the trade-off between the breakdown voltage and the ON-state resistance of integrated VDMOS transistors, an anti Junction Field Effect implant has been introduced for an 80V Smart Power platform based on a 0.35µm CMOS node. Optimized dose and energy allow a reduction of the resistance without significant impact on the breakdown voltage and the other integrated components of the technology.