In VDMOS device the anti-JFET concentration has important role for determining the breakdown voltage and on-resistance of the device. Because higher N-drift doping concentration can provide the very best on-resistance of the device but also decrease breakdown voltage. It also has a proportional relationship with threshold voltage degradation. In this paper, we report the anti-JFET implantation energy influence effect electric potential distribution, the highest impact ionization shifted from the silicon surface to deeper. It will have less hot carrier impact, and we have found higher breakdown voltage. The anti-JEFT implantation is critical for on-resistance off-state breakdown voltage optimization, However the high field and high impact ionization near the gate region will cause severe hot carrier Injection problem. The general expectation of high voltage VDMOS transistor is to have higher breakdown voltage, less degradation due to hot carrier injection and better on-resistance.
In this paper, we present new results on the width dependent hot carrier reliability and/or NBTI degradation for shallow-trench isolated (STI) on the uniaxial and biaxial strained pMOSFET devices. In p-MOSFET's, the interface traps generation at the STI-edge is enhanced for narrow width device. It was found that uniaxial (SiGe S/D) strained structure has comparable HC reliability with biaxial (SiGe-channel) device for long channel devices, while the drain current degradation is more enhanced for a reducing gate width in uniaxial narrow width strained device. This is related to the tensile stress in the channel width direction compared to the compressive stress of STI in biaxial strained SiGe channel devices. This tensile stress results in a much worse reliability. For NBTI reliability, it was found that the STI strains are strongly related to the channel width. This is a very crucial issue for the present and future CMOS ULSI using STI technologies in the narrow width strained devices.
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